Will dividing down an external clock add jitter?

[shffhsdfhse]

I read in the general timer manual for the STM32 (AN4013) that the external clock inputs (ETR, TI1, and TI2), which can be used for timer inputs, are synchronized internally with the APBx clock.

I just want to make sure I am understanding this correctly. Does this mean that even if an edge on ETR changes, it won't be "processed" until the next APBx clock? Or stated otherwise, that a clock output using the ETR pin as an input can only change on an APBx edge?

I was considering adding the hardware hooks to allow a dedicated external ADC clock to be divided down by passing it through the timer circuitry on the STM32. This would allow changing the sampling rate. The problem is that if it is really synchronized to the APBx edge, that is going to add a lot of jitter that will degrade the SNR of a high-speed/high-resolution ADC.

Do I have any other options to do something like this without synchronizing to the APBx clock, or am I better off just using external circuitry to divide sensitive clocks?

[S.Ma]

Would the clock reclocking mostly because of the timer registers which indeed needs to be accessed using MCU's ref clock?

[Tesla DeLorean]

There is most likely a 3 flip-flop resync circuit on the inputs, it has nyquist sampling behaviour.

You might want to look at the DCMI interface for clocking in 14-bit wide data on clocks of up to 54 MHz

[Piranha]

There is no information on particular MCU.

Maybe the solution uses SAI anyway and can just use it's MCLK divider? Or even use I2S_CKIN => SAI_MCLK without actually using SAI for it's main purpose!?