Why does the clock source for timer 3 seem to be double what I expect?

[RPear.1]

I have a Nucleo F103 board on which I'm playing with some code to generate a variable bit rate FSK data stream. The code seems to generate the right signal but at twice the expected frequency.

I have searched these boards and found one question for exactly the opposite, which hints that I may have misread the data sheets or not spotted some subtle detail. From what I can tell, timer 3's internal clock is the APB1 (low speed) clock. My code sets up :

• SYSCLK to 72MHz
• APB1 to 36MHz
• TIM3 pre-scalar to 35
• ARR to 116 or 204 and CCR to half that

I was expecting this to give me output signals with 116us or 204us cycle times - timer clocked at 1MHz - but I see half that, as if the pre-scalar is being clocked at SYSCLK instead of APB1.

What have I missed?

[waclawek.jan · Accepted solution]

Timers' clock is 2x APB clock, if APB divider > 1, see clock diagram in RCC chapter in RM.

(self-advertisement: nr 2 at efton.sk/STM32/gotcha)

JW

[RPear.1]

Ah! Yes, I can see that now. Fine documentation that it's only mentioned in a bit of small print on a busy (and thus zoomed out) diagram. Thanks.

[waclawek.jan]

It's told also in the narrative, "The timer clock frequencies..."

I admit it's easier found if you know it's there... :D

JW