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What is the detailed difference between VDD_FT and VDD?

Yang Yang
Associate II

Hello, ST expert

From the picture below, it showes that 5V tolerent GPIO connect to VDD_FT through a protection diode. But what is detailed difference between VDD_FT and VDD?

0693W00000NsWHdQAN.png 

BR

Yang​

1 ACCEPTED SOLUTION

Accepted Solutions
KnarfB
Principal III

FT stands for five volts tolerance here. For FT IO pins, +5V at the input and VDD=3.3V would put the upper protection diode in pass mode and may damage the circuit. Therefore, the internal implementation for FT and non-FT pins is slightly different.

Perharps there is an explanation in the foot note (1) of your drawing, but you did not cite the source.

See AN4899 Application note "STM32 microcontroller GPIO hardware settings..." for details.

hth

KnarfB

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8 REPLIES 8
KnarfB
Principal III

FT stands for five volts tolerance here. For FT IO pins, +5V at the input and VDD=3.3V would put the upper protection diode in pass mode and may damage the circuit. Therefore, the internal implementation for FT and non-FT pins is slightly different.

Perharps there is an explanation in the foot note (1) of your drawing, but you did not cite the source.

See AN4899 Application note "STM32 microcontroller GPIO hardware settings..." for details.

hth

KnarfB

Hello, KnarfB

Thanks for your quick reply. For the scene VDD is not present, but the GPIO pin is drived 3.3V from external part, ​what would happen? The injection may damage the device?

I found our custom board may get this issue. The GPIO pin shows only tens of Ohm resistance to GND. And MCU can not work again.

BR

Yang

Correct, applying a voltage to a GPIO without a supply voltage being applied to VDD is an impermissible condition and can lead to destruction due to the injection current.

Regards

/Peter

In order to give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

Hello, Peter

However still I have problem with this issue. From AN4899 Fig 16, the injection appears when VDD is not present. But VDD and GND is not the same net. How the injection current can get directly from VDD pin to GND?

0693W00000NsXKYQA3.png

If there is no voltage at VDD, the parasitic pn junctions are polarised in the forward direction. That causes an injection current flowing from the GPIO in the direction of the internal VDD, thus supplying the MCU via the GPIO, so to speak.

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Hello, Peter

Maybe I don't describe my concern clearly. ​ I mean the current comes from VDD pin of MCU and GND. There should be not a small resistance often, e.g. several Kilo Ohm. So the injection current should no more than a couple of milli Ampere, this small current can still damage MCU?

0693W00000NsYSOQA3.png 

VDD is usually not only connected to the MCU, but to the surrounding circuitry, which is also connected to 3.3V. So when there is no voltage at VDD, there is a path for the current as marked in pink in the picture or by you in green.

The connection of VDD and GND is meant symbolically there, because at least the capacitors connected to VDD represent a short circuit for some time. The resulting current from the GPIO via the block called ESD protection in the picture, VDD to GND can therefore be very large and destroy at least this GPIO pin. Therefore, it is imperative that the maximum values for the injection current specified in the data sheet are adhered to.

Regards

/Peter

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Uwe Bonnes
Principal III

The way the current flow has no resistance in the Kiloohm range. It involves forward-biased diodes with a sharp rise in current with little additional applied voltage. Getting above the maximum allowed values is doomed for destruction of the device.