What is SAI "Error between selected"? (CubeMX bug?)

[TDJ]

Today I spent some time to fine-tune SAI clock to get standard 22.05kHz sample output rate.
However, I do not understand why CubeMX states that "Error between selected" is 0.22%.

What is "Error between selected"? Why this error is zero when selected frequency actually differs from the desired value by 0.05kHz? Am I missing something?

 

 

 

[Pierre_Paris]

Hello @TDJ,

Thank you for bringing this issue to our attention.

I confirm the issue and I reported internally.

Internal ticket number: 165344 (This is an internal tracking number and is not accessible or usable by customers).

Thank you for your contribution in STCommunity ! 🙂

Pierre

[AScha.3]

@TDJ  , i can confirm: the % deviation is the cause of many a good laugh . 

Whoever programmed this , has a big problem with with 3rd class mathematics. just laugh briefly and hope,

the calculated frequency is right. (which seems to be ok in my tests).

what is really bad in the SAI frequency setting is the divider , in my opinion.

almost impossible, to find a clock/divider setting, that makes 44100, 48000, 96000, 192000 Hz possible.

so i set it to slave + transmitter and the dac (ES9038) generates the sampling frequency at any value (32bit frequency value).

[LCE]

@AScha.3 ES9038, wow, never heard of that DAC and that company. Thanks for mentioning that device, so that I found another audio converter alternative (mostly ADCs, for industrial purposes, but audio range).

[AScha.3]

🙂

the ES9038 is at the top group of audio dacs of the world...

and they have also ADC; mouser  has ES9826Q ; 

[TDJ]

@AScha.3 I agree. Luckily, by fine-tuning PLL one can get really close and 0.001 HZ difference should no be audible even to musicians blessed with perfect pitch. That remains to be tested yet. Another approach I tried was using PLL 441x multiplier but I could not find settings within allowable frequency limits. So the current approach, that is, PLL3 clocked by 16MHz MSIS CRS-SYNCed with very stable LSE 32.768 kHz, may be the best one.

[AScha.3]

i (until now) never used the fractional setting in pll, because the jitter on the STM cpu is anyway not great, a cheap ESP8266 is better. And the fractional part...what could it do? switch the pll divider a step an back, in sigma/delta way. i cannot imagine, this will make a useful clock...did you check the jitter?

and for other dac, SAI in master transmit, i used:

with HSE 8M crystal , gives in Cube:

0,086% says my calculator. 🙂  (44100 / 44062 = 1,0008624) too difficult for STM software.

thats ok, so far.

[LCE]

Concerning STM32 PLL and jitter:

I have used a few Nucleos (G4, F767, H723, with the ST-Link MCO as clock source) and a H735-DK and the PLL as source for SAI / I2S. 
I have not seen any bad impact on signal quality, with TX-SPDIF and with 115dB SNR audio ADCs (sampling rate up to 200 kHz).

I think the jitter would have impact on non-oversampling ADCs.

[Piranha]

To be exact, it's the inverse: 44062 / 44100 - 1 = -0,0861678 %. 😉

I looked at the CubeMX calculated "error" numbers and realized what they are calculating. A warning - sit down so that you don't fall of your chair!

For 44,062 kHz: 62 / 44000 = 0,14 %

For 22,049 kHz: 49 / 22000 = 0,22 %

For 22,000 kHz: 0 / 22000 = 0 %

A pure kindergarten...

@TDJ , the 16 MHz / 4 * 127 / 45 gives a frequency, which deviates from your ideal target frequency by -63 ppm. Humans can detect a pitch variation of 0,3 % (3000 ppm) at best. And that is for a variation, not a constant offset! In other words - there is absolutely no point in using a fractional PLL mode and increasing the jitter unnecessarily.

[AScha.3]

>For 44,062 kHz: 62 / 44000 = 0,14 %

1. great reverse engineering (i never would have this idea...)

2. you could be a great psychoanalyst also! (because this is beyond any mathematical explanation ...)

3. maybe this is from one of the great java programmers at STM, who is used to a compiler, that automatically fills in missing variables and not complain about some so small errors.