What are the correct FLASH page numbers for STM32G0 dual bank devices? It looks like there's an inconsistency between the reference manual and the Nucleo FLASH examples included in the STM32G0 Cube G0 package.

[Markus8494]

In the datasheet (RM0444) for 512k dual bank devices, it looks like the last page of bank 1 is 127 and the first page of bank 2 is 256 (see section 3.3.1)

The flash control register (see 3.7.5) says, the valid values for PNB is from 0 (page 0) to 0x17F (page 383).

In the STM32G0 HAL FLASH example for Nucleo G01BRE, however, the C procedure to calculate the page from a given address calculates page 0 for the first bank 2 address (0x0804'0000).

static uint32_t GetPage(uint32_t Addr)
{
  uint32_t page = 0;
 
  if (Addr < (FLASH_BASE + FLASH_BANK_SIZE))
  {
    /* Bank 1 */
    page = (Addr - FLASH_BASE) / FLASH_PAGE_SIZE;
  }
  else
  {
    /* Bank 2 */
    page = (Addr - (FLASH_BASE + FLASH_BANK_SIZE)) / FLASH_PAGE_SIZE;
  }
 
  return page;
}

Used STM32 Cube G0 package version: 1.5.0

Which one is correct?

[Andreas Bolsch · Accepted solution]

https://community.st.com/s/question/0D53W00000WbZ3ISAV/flash-page-numbering-in-rm0444-and-0454-correct

[Imen.D]

Hello @Markus8494​  and welcome to the Community :)

Thank you for rising this up.

The RM is incorrect and pending correction.

I've just checked the status of this request and asked the appropriate owner to correct this error in the coming release of the RM.

Thanks for your contribution.

Imen

[Markus8494]

Hello,

thank you both for your quick and clarifying response.