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Hello,I am currently developing a Bootloader for a STM32H562. The Bootloader checks, if there is a valid application present by calculating a checksum over the application area. To avoid getting ECC errors during the checksum calculation, I disable t...
Hello,I am currently evaluating the STM32H562 device. This devices has an ICACHE (instruction cache) module.Does it make sense to enable both, the ICACHE module and the FLASH prefetch buffer? In the past I already worked with the G0, G4 and F4 series...
I am currently implementing a UART communication on a STM32F1. As I understand from the manual, the ORE bit does block all further Rx until it is cleared but the other error flags (PE, NE, FE) do not block Rx when set.How is the behaviour of the UART...
I have a very strange behaviour when using the (on-board) ST-Link debugger on the STM32G0B1 Nucleo board using the Flash Programming example contained in the STMCubeG0 package (v1.5.0).I use Keil MDK IDE v5.36, CMSIS- & STM32G0 device support package...
In the datasheet (RM0444) for 512k dual bank devices, it looks like the last page of bank 1 is 127 and the first page of bank 2 is 256 (see section 3.3.1)The flash control register (see 3.7.5) says, the valid values for PNB is from 0 (page 0) to 0x17...
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