Weird ADC failure STM32F091, any ideas

[Oliver Sedlacek]

We've been building a PCB with four STM32F091s on each PCB and we've built about 50 units by now (over about 3 years). I have now seen three PCBs where the ADC readings are 'bad' on two of the four micros. By 'bad' I mean conversion values are 30% ish low.

With the design having been stable for quite a while, the chances of uncovering a new bug seem slim, but chip damage seems even more unlikely. The fault also 'went away' on one of the PCBs, so more evidence that it's not damage.

The ADC reference is VDD 3.3V on all the chips, and they all run the same code.

Anyone got any thoughts?

[Oliver Sedlacek]

I was using VDD and getting these 30% discrepencies. Using IntVRef the results are much better, probably within spec.

Thanks for the reminder on sampling control, having read the ADC section many times I was aware of this. Quite why I need such a long sampling time is still a mystery

[waclawek.jan]

> I was using VDD and getting these 30% discrepencies. Using IntVRef the results are much better, probably within spec.

That would indicate problem with VREF+.

Which package are you using, is it a separate VDDA/VREF+ or the common one? [EDIT] OK had a look into the datasheet, and it appears that there's no 'F091 (probably no 'F0xx) with separate VREF+ pin. Didn't know that.

Don't you filter VDDA/VREF+ using a choke or RC filter?

JW

[Oliver Sedlacek]

Good decoupling, ground and VCC plane, ferrite between analogue and digital, just basic stuff. The mystery is why we haven't seen it historically on the bulk of the boards. I'm suspicious that they are grey market chips, maybe rejects that pass superficial testing. Going from spot on to 'quite a long way off' is odd.

[raptorhal2]

Your comment about sampling time improving the result suggests that you are sampling a high resistance, possibly a resistive network. Interaction between signals in a resistive network fed by a common supply voltage can produce puzzling results. Describe your signal sources.

If you haven't done so, read AN2834 for an explanation of when longer sampling time improves accuracy.

Cheers, Hal

[waclawek.jan]

> ferrite between analogue and digital

Try removing/shorting it.

Results may get noisier, but the real question is, whether this removes the gross 30% error.

JW

[Oliver Sedlacek]

My unkown signal is between1k and 10k source resistance, less than the data sheet max of 50k. The mystery is why Vref Int measurements change with sampling time as I would have thought that this is a relatively low impedance signal.

[waclawek.jan]

> between1k and 10k source resistance

That's not exactly low, see sampling time calculation formula in DS.

> The mystery is why Vref Int measurements change with sampling time as I would have thought that this is a relatively low impedance signal.

It is a relatively high impedance signal and datasheet requires a min.4us sampling time.

JW

[Oliver Sedlacek · Accepted solution]

I really appreciate the help I've had on this problem, so thanks to you all.

So what was the problem down to? Why were so many micros working before this problem started to appear?

Mechanical stress! The boards are bolted to a heatsink, so there's a thermal pad under most of it. Recently a thicker pad was being fitted and where the PCB overhangs the pad (not ideal with hindsight), pulling down the bolts was bowing the PCB. The chips don't like it!

[LCE]

Thanks for the feedback!

[waclawek.jan]

Humm, I didn't expect that...

Thanks for coming back with the solution. Please select your post as Best so that thread is marked as resolved.

JW