Want to store data in SRAM D2 domain, what is missing to avoid Hard fault?

[Joerg Wagner]

Instead of using DTCMRAM or SRAM D1 domain via AXI, I set up the linker file to use D2.

In system_stm32h7xx.c I added the lines:

  /* Change the switch matrix read issuing capability to 1 for the AXI D2 target (Target 2 and INI2) */
  *((__IO uint32_t*)0x51003108) = 0x00000001;
  *((__IO uint32_t*)0x51043108) = 0x00000001;

But executing

/* Call static constructors */
    bl __libc_init_array

in startup_stm32h743xx.s a Hard Fault is thrown.

What is missing to have normal data stored in D2 domain?

Thank you for any tipps.

[Tesla DeLorean]

>>What is missing to have normal data stored in D2 domain? Thank you for any tips.

Enable the D2SRAM clocks? In SystemInit() prior to __libc_init_array call, or in startup.s

ie

 /* Enable D2 domain SRAM3 Clock (0x30040000 AXI)*/

 __HAL_RCC_D2SRAM3_CLK_ENABLE();

 /* Enable SRAM1/SRAM2/SRAM3 clocks on D2 domain */

 __HAL_RCC_D2SRAM1_CLK_ENABLE();

 __HAL_RCC_D2SRAM2_CLK_ENABLE();

 __HAL_RCC_D2SRAM3_CLK_ENABLE();

[Tesla DeLorean · Accepted solution]

Reset_Handler:  
  /* Enable D2SRAM clocks in RCC_AHB2ENR */
  ldr r0, =0x580244DC
  ldr r1, [r0]
  orr r1, #0xE0000000
  str r1, [r0]
...

[Joerg Wagner]

Great! Mastering the beast.

Any other places don't work, just in Reset_Handler only.

I spent too many hours with it, thank you.

[Tesla DeLorean]

If you get the Initial Stack Pointer set to unusable memory you're pretty much dead in the water. You can put a DTCMRAM address in the vector table, and subsequently load the SP with desired location/region

[Joerg Wagner]

But I'm wondering about the necessity. Page 104 in RM0433 says:

Upon reset, clocks to blocks such as peripherals and some memories are disabled (except
for the SRAM, DTCM, ITCM and Flash memory).

And if I use D1 SRAM for data and work with Ethernet in D2, it works without enabling the clock for D2.

[Tesla DeLorean]

It is likely enabling some place else, I'd chase it down, but have more productive things to do.

[Tesla DeLorean]

Ibrahim Abdalkader had identified the issue here, but thread closed, so props to him. https://community.st.com/s/question/0D50X00009XkWvBSAV/stm32h7-and-heap-location

I had grepped the code base for the __HAL_RCC_D2SRAM, ST has is scattered hither-and-far, strategically it should be early, or in SystemInit() provided no dependencies on it for a stack, etc.

#ElephantInTheRoom I just remember where to look and why it is important.

[Singh.Harjit]

​I haven't seen this snippet of code before for the STM32H7 series part:

/* Change the switch matrix read issuing capability to 1 for the AXI D2 target (Target 2 and INI2) */

*((__IO uint32_t*)0x51003108) = 0x00000001;

*((__IO uint32_t*)0x51043108) = 0x00000001;

Can you share details around it? Is it for an errata item? Thanks.

[HaiHuynh08]

In system_stm32h7xx.c, there is a coding line:

#if defined (DATA_IN_D2_SRAM)
  /* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
  RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);

It would enable SRAM in D2.