It is in Table "AXI interconnect register map and reset values", Reference Manual. This table shows Offset of AXI_TARG2_FN_MOD (0x3108) and AXI_INI2_FN_MOD (0x43108). Because the base address of Global Programmer View (GPV) is 0x51000000 (as Table "R...
In system_stm32h7xx.c, there is a coding line:#if defined (DATA_IN_D2_SRAM)
/* in case of initialized data in D2 SRAM (AHB SRAM) , enable the D2 SRAM clock (AHB SRAM clock) */
#if defined(RCC_AHB2ENR_D2SRAM3EN)
RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM...
Hi Sirlsaac,I also have this problem. I solved it by:Replacing DTCMRAM with RAM_D1 (as DMA of SDMMC1 only works on RAM D1) in file STM32H743XIHx_FLASH.ld. Correct code for file STM32H743XIHx_FLASH.ld (I replaced at lines 27, 44, 55:(/* Specify the me...
