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Using classical CAN with FDCAN controller on STM32H743VIT6

LSH
Associate II

Hello. I have three question about using classical CAN frame with FDCAN controller.

I am using STM32H743VIT6 MCU on my PCB.

 

1. If system clock(label in ioc file: SYSCLK) is too low, can it make impossible to use CANbus?

2. If I using only classical CAN frame, does Nominal bit timing parameter(Nominal Sync Jump Width, Nominal Prescaler, Nominal Time Seg1/2) only consider and Data bit timing parameter ignored? or both bit timing parameter use for CAN 2.0 communication?

    2.1 I am using KVASER Bit Timing Calculator to set timing parameter. what is appropriate sample point value for STM32H743?

    2.2 There is Tseg1, Tseg2, SJW at KVASER Bit Timing Calculator for CAN FD. Does Tseg1 = Time Seg1, Tseg2 = Time Seg2 and SJW = Sync Jump Width?

 

3. If I using only classical CAN, may I use CAN transceiver which is not supporting FDCAN?

(I already make PCB and I use CAN transceiver which didn't supporting FDCAN...)

 

Thank you.

 

1 ACCEPTED SOLUTION

Accepted Solutions
SofLit
ST Employee

Hello,

  1. 1. If system clock(label in ioc file: SYSCLK) is too low, can it make impossible to use CANbus?

     Too low? how much? and why?

  2. If you are in Classical CAN config, Data timings are ignored.

    2.1 The sample point position depends on the bitrate:

    SofLit_1-1707486825476.png

     

    2.2 There is Tseg1, Tseg2, SJW at KVASER Bit Timing Calculator for CAN FD. Does Tseg1 = Time Seg1, Tseg2 = Time Seg2 and SJW = Sync Jump Width? --> Yes
  3. The choice of the transceiver depends on the bitrate you will reach independently from the usage of classical CAN or FDCAN. If you are using classical CAN you need a transceiver that can reach up to 1Mb/s (of course if you're reaching this bitrate).
To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

View solution in original post

3 REPLIES 3
SofLit
ST Employee

Hello,

  1. 1. If system clock(label in ioc file: SYSCLK) is too low, can it make impossible to use CANbus?

     Too low? how much? and why?

  2. If you are in Classical CAN config, Data timings are ignored.

    2.1 The sample point position depends on the bitrate:

    SofLit_1-1707486825476.png

     

    2.2 There is Tseg1, Tseg2, SJW at KVASER Bit Timing Calculator for CAN FD. Does Tseg1 = Time Seg1, Tseg2 = Time Seg2 and SJW = Sync Jump Width? --> Yes
  3. The choice of the transceiver depends on the bitrate you will reach independently from the usage of classical CAN or FDCAN. If you are using classical CAN you need a transceiver that can reach up to 1Mb/s (of course if you're reaching this bitrate).
To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
LSH
Associate II

Hello SofLit.

Thank you for your reply!

 

I am using 12MHz SYSCLK and 40MHz for FDCAN. Is it too low?

 

I have to make it low as possible for low power consumption. (but I can't change MCU for low power.)

Therefore, If there is clock under limitation for system clock frequency, please let me know the minimum system clock frequency for CAN communication.

LSH_0-1707524234436.png

LSH_1-1707524254149.png

 

Thank you again.

See my reply in this thread: https://community.st.com/t5/stm32-mcus-products/stm32h743vi-fdcan-didn-t-works-as-classical-can/td-p/638308

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.