timings of the FMC SDRAM controller operations in STM32F446xx

[barton_hill]

I'm trying to understand the operation of the STM32F446xx family of microcontrollers. I'm reading the reference manual that's available here: https://www.st.com/resource/en/reference_manual/rm0390-stm32f446xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf. I'm struggling to understand the timing of how the FMC SDRAM controller reads the data it anticipates and stores them in the FIFO. I have the following questions:

1. On page 313, in the description of the RPIPE bits, it is stated, "These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency." Which clock does KCK_FMC refer to? And how are KCK_FMC and SDCLK related? I couldn't find KCK_FMC mentioned anywhere else in the manual.

2. On page 306, it is stated, "The FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to store data read in advance DURING the CAS latency period and the RPIPE delay ..." I'm confused as to how data is read DURING the CAS latency period. Wouldn't the data from the SDRAM be available to read only AFTER the CAS latency period?

[KDJEM.1 · Accepted solution]

Hello @barton_hill and welcome to the community,

The interest of the RPIPE delay is to add few cycles before sampling the data while configuring correctly the CAS latency. 

When inserting the RPIPE delay, since the is read FIFO fetching data during the CAS latency cycles, adding RPIPE delay will add other cycles and allows to fetch more data in Read FIFO. We provided the formula of number of anticipated data based on the RPIPE and CAS latency configuration.

For SDRAM read timing, I recommend you referring to DS10693 Rev 10 Table 100. SDRAM read timings and Table 101. LPSDR SDRAM read timings.

Thank you for bringing the KCK_FMC issue to attention our attention. 

I reported internally for verification and correction.

The "KCK_FMC" will be replaced by "HCLK".

Internal ticket number: 214099 (This is an internal tracking number and is not accessible or usable by customers).

Thank you.

Kaouthar

[barton_hill]

Hi Kaouthar,

Thank you so much for the clarification!! I thought a little bit more and am wondering about the use of the RPIPE bits in the FMC_SDCRx registers. Would you be able to please give me examples of situations under which configuring an additional delay beyond CAS latency using the RPIPE bits would be useful?

Thanks,

Barton

[KDJEM.1]

Hello @barton_hill:

The RPIPE could be useful in case of some hardware issue, delay added due to PCB, you can compensate this delay by adding few cycles before sampling the data. But a good PCB you will not have any issue.

Thank you.

Kaouthar