I'm trying to understand the operation of the STM32F446xx family of microcontrollers. I'm reading the reference manual that's available here: https://www.st.com/resource/en/reference_manual/rm0390-stm32f446xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf. I'm struggling to understand the timing of how the FMC SDRAM controller reads the data it anticipates and stores them in the FIFO. I have the following questions:
1. On page 313, in the description of the RPIPE bits, it is stated, "These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency." Which clock does KCK_FMC refer to? And how are KCK_FMC and SDCLK related? I couldn't find KCK_FMC mentioned anywhere else in the manual.
2. On page 306, it is stated, "The FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to store data read in advance DURING the CAS latency period and the RPIPE delay ..." I'm confused as to how data is read DURING the CAS latency period. Wouldn't the data from the SDRAM be available to read only AFTER the CAS latency period?
