cancel
Showing results for 
Search instead for 
Did you mean: 

The MCU requires NRST to be toggled after power on

RobertK
Associate II

Hi all, I have a problem with a new version of an existing PCB using the STM32F334C8T6 microcontroller.

Known working code is loaded onto the new PCB, power is applied and the MCU starts up the clock and then seems to sit idle. If the NRST pin is then driven low and released the MCU starts up and begins operating normally. Holding NRST low on power up and then releasing it after a duration does not work, the MCU must attempt to start up and fail first. NRST is connected to a 10kΩ to +3V3 and a 100nF to 0V. BOOT0 is connected to a 10kΩ to 0V.

PXL_20230922_103355658.jpg

The signals here (top to bottom) are:
old PCB +3V3
old PCB NRST
new PCB +3V3
new PCB NRST
While both boards were powered at the same time the new board has an additional SMPS stage which adds a small delay to the rise of the +3V3 rail.

PXL_20230927_100625674.jpg

The signals here (top to bottom) are:
old PCB NRST
old PCB 8.000MHz crystal
new PCB NRST
new PCB 8.000MHz crystal
I've gone through a couple of stages of being suspicious of the clock as it gets enabled by the code, but then the code seems to stop/stall. However the scope traces don't show any significant problems. I've also compared the clock signal after the reset with the MCU running code and it looks identical to the above scope trace where the MCU is stalled. 

The new PCB does have a different 8.000MHz crystal so I may have got the load capacitors wrong. The new board is using this crystal from JLC with 2x 22pF 0402 C0G load capacitors. Is this correct? Should I be using a different value?

There are other minor differences between the two boards, but nothing that would suggest this issue. e.g. some pins no longer have a 1kΩ resistor linking them even though one pin was never enabled/driven in the code.

I'm running out of hair to tear out so welcome any suggestions of what the issue might be or further debugging steps. Thanks!

19 REPLIES 19

I thought I'd managed to narrow the problem down to these lines of code:

InitPinOut( DRV_SLEEP_N );		
InitPinOut( DRV_RESET );		

//SPI
InitPinOut( DRV_SPI_MOSI );
InitPinIn( DRV_SPI_MISO, GPIO_PULLUP );		//TODO check DRV spec
InitPinOut( DRV_SPI_CS );		
InitPinOut( DRV_SPI_SCK );		
spi.format(16, 0);     // 16 bit, mode 0
spi.frequency(100000);

//Inputs
InitPinIn( DRV_FAULT, GPIO_PULLUP);			//TODO pullup needed??
InitPinIn( DRV_STALL_N, GPIO_PULLUP);

However none of these seem likely to cause the issue I'm seeing where the MCU seems to reset and then lock up.
I loaded the original firmware on again just to confirm I'm still seeing the issue and it worked. The MCU booted up from power up, ran the code and operates exactly as it should. I have a second board that also exhibited this issue so now my debugging has moved over to this second board. Having the problem magically fix itself worries me greatly.

ONadr.1
Senior III
I would try to cool or heat the board and see if that affects the occurrence of the problem. I would also measure the current of the power source, if the MCU does not fall into some kind of power saving mode. And maybe it wouldn't be a bad idea to activate WDT before setting MCU clock . Although it does not solve the root of this problem, it could solve bad behavior.
 
LCE
Principal

> ... Having the problem magically fix itself worries me greatly.

But haven't you played with the crystal and the caps? Or did you put it back into the original state?

Edit: maybe the originally assembled crystal caps were not what they should be?

Hi LCE and others,

You're right! So far I've changed the crystal caps on 5x boards to 6.8pF, 4x of these boards now start up pretty reliably with the 5th still having the issue. It does still occasionally happen on the 4x 'working' boards. So I guess my next question is, how do I measure 'good' for crystal capacitors?

I've gotten the updated value of 6pF from this formula: C1 = C2 = 2 * (CLoad – Cstray) from here: https://microchip.my.site.com/s/article/Calculating-crystal-load-capacitor. The JLC/LCSC part listing says CLoad = 8pF, the consensus seems to be that Cstray is usually around 5pF so I calculate 6pF, and the closest value is 6.8pF. However this is still giving me spotty start up issues, especially when cold (like ~5°C)

Thanks!

Show us the relevant portion (i.e. around crystal) of PCB layout.

JW

GLASS
Senior

Avoid probing directly hse quartz.

Try a very simple sw based on hsi and not hse to only toggle a gpio.

Be sure of all powering, try to catch with scope very short undervoltage.

Have a look to nrst pin. Try without any capacitor on this pin.

What about option bytes? Try without BROWNOUT reset.

Okay, it's a 4 layer, 1.6mm thick FR4 board with 2oz copper per layer PCBA.

Top:

RobertK_0-1698319796386.png

Crystal is a 3225 package, left middle. I tried to route the osc pins as a differential-ish signal. Tried to surround them with GND.

Inner 1:

RobertK_1-1698319821990.png

Pour of GND.

Inner 2:
RobertK_2-1698319837612.png

Pour of +3V3

Bottom:
RobertK_3-1698319859407.png

Mostly a pour of GND with some traces. NRST runs under the crystal, and CONSOLE_TX/CONSOLE_RX/TIMING_PULSE are all unused signals crossing at 90deg under the MCU pins.

I think I've done a pretty good job here and there shouldn't be anything iffy about the layout.

LCE
Principal

That looks good, only one question, what is the signal with the via from +2 pins north of the OSC pin? Just curious, shouldn't matter before start up.

 

That's TIMING_PULSE. As of yet, it's not pulsing, so it's just held high with 10kΩ pullups to +3V3.

RobertK
Associate II

It's been a while but I am still having issues!
After testing a few PCBs with 6.8pF capacitors I thought this was the fix and ordered another 30x PCBs with 6.8pF capacitors.

5x of these boards do not work, on power up they are non-responsive then once reset they activate and respond.

I decided to brute force the solution a bit:

Board4.7pF5.6pF6.8pF8.2pF10pF12pF15pF
ANot testedNot testedYesYesYes-untestedYesNo
BNot testedNot testedYesYesYes-untestedYes-untestedNot tested
CNot testedNot testedYesYesYes-untestedYesNot tested
DNot testedNot testedYesYesYes-untestedYes-untestedNot tested
ENot testedYesYesYes-untestedYes-untestedYesNot tested
FNoNot testedNoYesYesNoNo
GNot testedNot testedNoNoNoNoNot tested
HNot testedNot testedNoNoNoYesNot tested
INot testedNot testedNoYesNot testedNot testedNot tested

That seems to suggest that 8.2pF might be a better capacitor. However I'm worried that the thresholds for these capacitors is that tight. Most of the threads I can read about this seem to suggest that the tolerances should be pretty wide.

Is the low load capacitance (8pF) or the high ESR (<120Ω) the reason why this is being so tricky?