Systick and I2C DMA -blocked by EMP(Electro Magnetic Pulse) Attack (STM32F030R8T6TR)

[H1]

My work environment is heavily disturbed by EMP which particularly has frequency of 2.44GHz. I measured the frequency and 2.44GHz is most frequently affecting, but 900Mhz range has other influences to MCU operation.

Sometimes, ST-LINK V1 and V2 is disabled and shows malfunction state - (cannot stop running or cannot start debugging, cannot download hex) when such EMP distrubance attack is escalated. The purpose of such attack is to usurp the engineering efforts and sometimes, to steal the business opportunity by infinitely delaying the project end.

My system is composed of 2 parts : Atmel ATMEGA128 based sensor concentrator and STM32F030R8T6TR based sensor collector client.

According to the strength of EMP attack, in the high radiation range, JTAG MKii and ST-LINK is both malfunctioning. That is, with both device, the debug and commnunication fails with target system. And in medium EMP strength, internal DMA, UART, Timer, Systick is heavily disturbed and seems to stop operating.

Following article shows, EMP attack can disable the operation of electronics including the MCU functions. Does ST have any counter-measure for such hostile attacks against ST-branded-semiconductor-based electronics products?

https://www.lifewire.com/would-your-car-survive-an-emp-attack-3903248

Or does ST chips include RF sensor circuit to react for forced-stop commanding RF signal of enforcement personnel for the purpose to stop dangerous operations of electronics, such as terror or criminal attack weapons?

If so, ST should provide guidance of EMP level in Absolute Operation Condition of datasheet, in which ST chip can operate safely, as well as test method (such as IEC specification) to measure such EMP influences. Can ST Microelectronics provide such document.

In South Korea where I am located, such hostile activity can depress and frustrate the interest of developers, who want to apply ST chips to electronic product design.

In my previous project of Auto Sliding Door controller, this project included STM8 series controller. This controller also heavily was affected by such EMP attack, arising security problem such as forced-opening door, or door close failure.

Waiting for your urgent and serious comment for such critical issues caused by EMP attack.

 

[Piranha]

These type of problems are system level problems and cannot be solved with a single chip. It requires appropriate schematic, PCB, enclosure, wires etc.

[H1]

What I mean in the above posting is the clarification regarding the guidance of EMP level in Absolute Operation Condition of chip datasheet, in which ST chip can operate safely, as well as test method (such as IEC specification) to measure such EMP influences. ST does not provide any ratings in Absolute Operation Condition for such EMP distubances, but such testing method and clear max, min limit for safe operation should be provided to estimate the stability of the system. Such information is needed to define exact working limit for the product design, even though optimistic shielding enclosure or shielding circuits are implemented in the product design. Without such definite declaration for EMP immunity for ST chips, the product design cannot become a predictable system, but just a rough-estimated product.

I personally raised such issues to ST staffs, for it will surely become a very serious security point in the near future to protect the safety of all people who use such design.

[RMcCa]

Building EMP hardened equipment is a whole field by itself, usually military.

You say you are under EMP attack? It's not easy building large enough EMP generators to really cause any damage and i would think your government would be very interested in finding and stoppin​g it.

Strong enough EMP pulses will fry the front end of radios and lab-sized EMP generators can cause sparks to leap out of electrical outlets on the other side of the building. Don't ask me why i know....

[H1]

Dear RMcCa

For EMP attacks, I would like to classify those attacks into 2 categories. Category 1 is the EMP disturbance caused by commercial radio devices, such as the WIFI circuit of Mobile phone, WIFI router, LTE repeater, or Walkie-talkies. Catergory 2 can be high-powered equipments which have a quite big power than above Category 1 and requires the authorization of government authorities. For Catergory 2, there would be no proper commercial measures to stop it. But for Category 1, even though those equipments are usually certified by radio control authorities, it still can affect to the operation of ST chips. For this reason, ST can provide the maximum rating of EMP immunity for incoming EMP with low power level. And proper digital signal output through a port pin, should indicates excessive EMP radiation is incoming to ST chip, which is enough to disable the normal operation of ST MCU.

[S.Ma]

I think it is a bit similar to rad hard expensive part going to satellite and less susceptible to solar flares.

Most electric susceptibility boils down to current loops, say between signal and supply and ground, oscillator, DCDC converters.

ESD body model, CDM, EOS are related to the topic.

If you use CSP vs QFP144 your inductances are different with same silicon inside.

If your applucation can work 1.7 to 3.6v range with internal wait states anf sysclk relaxed, it coukd help too, maybe set the supy at 2.5. For esd or other things, when possible, use external setial 1kohm resistor on inputs, use open drain outputs when possible, or external esd protections like the ones for usb.

Current loops area during transient should be minimized. Also add pcb made decoupling caps close to the chip as smd caps are slow. 300ps per inch...

Again, not an expert in this field... Surely someone can offer better suggestions