STM32U595 USB_CoreReset() does not work with clock source set to HSE/2

[Lukasz Nowak]

I am using a 32 MHz crystal with STM32U595 and I noticed that selecting HSE/2 (16 MHz) as OTG HS Clock Mux source results in USB_CoreReset() getting stuck in the loop waiting for the reset to complete:

  do
  {
    count++;

    if (count > HAL_USB_TIMEOUT)
    {
      return HAL_TIMEOUT;
    }
  } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);

Other configurations of OTG HS Clock Mux, appear to work:

- PLL1P configured to 16 MHz

- HSE with OTG PHY reference clock selection set to 32 MHz

Here is my complete clock tree, which doesn't work - just switching OTG HS to PLL1P resolves the issue:

[FBL]

Hi @Lukasz Nowak 

You mean you tried switching to the PLL1P clock source to resolve your issue? Check the PLLM (PLL1M) with a 1 divider or consider decreasing the power supply VOS. For the proper operation of the interface, an accurate clock is essential. Increasing the PLL divider may impact precision and stability. I suspect the issue lies with the precision of the interface clock, not the kernel clock.

[Lukasz Nowak]

Hi @FBL 

The HSE clock is a 32MHz 10ppm crystal.
The only input to OTG HS Clock Mux which does not work is HSE/2 at 16MHz.
Using HSE input at 32MHz works and PLL1P at 16MHz also works.

btw with a 32MHz input, PLLM divider cannot be 1 - it exceeds the maximum frequency.

If you need me to provide any additional information, do let me know. Thanks.

Lukasz

[FBL]

Hi @Lukasz Nowak 

Strange behavior! I'm using HSE input at 16MHz and it works without issues! So, if you are suspecting the divider of HSE feeding the kernel, I will change the oscillator and try to reproduce on my end.