Hardware: B-U585I-IOT02A dev kit
SPI1 configuration:
- Master mode
- 8-bit data size
- NSS hard output
- Tx only (2-lines)
- MSB first
- PCLK: 160 MHz; Baud Prescaler 32 yields SPI sck of 5MHz
- no CRC
- fifo threshold 1-data
- Master Keep IO State enabled
- RDY management internal (ie RDY disabled)
When running long-term reliability tests between 2 devkits, we occasionally will detect a transmission error which has been determined to be due to missing the final byte of the transfer. When viewed on a scope, only the first 3 SCKs are provided for the final byte then the transfer is ended (NSS goes high immediately after the 3rd SCK). This occurs when using HAL_SPI_Transmit(). Even when decoupling the NSS signal from SPI hardware control and driving it manually with software, the failure always presents itself as the Tx only shifting the first 3 bits of the last byte. We have tried slower and faster SCK baud prescalers with the same result. I would note that this problem occurs after many hundreds of thousands of successful transfers and always on the final byte of the transfer.
Looking for any ideas of what could be going on as it is unclear from the reference manual what could cause a transfer to end abruptly like this. The errata does not have any notes which seem to be related to this. It is not easy to post actual example code but the SPI driver code is highly modeled after Cube example code provided. But happy to provide any other information that might be relevant.
Thanks in advance for any help!
