STM32U575: ADF1 does not work when selecting PLL3Q for clock source

[coppercrimp]

I’ve been working with the STM32U575RIT6 and it’s ADF1 peripheral. I have a digital MEMS microphone connected to the ADF1 pins on the micro. I’ve been following the “ADF_AudioRecorder” example provided with the STM32Cube firmware. I can get the code to work just fine when selecting the MSIK clock for the ADF1 peripheral, but the peripheral stops working when I select PLL3Q for the clock source. See the attached screenshots from CUBEMX.

PLL3Q clock is generated from an external crystal (HSE). I’ve verified that the crystal is working on my custom board.

Can someone help explain why I’m having this problem? Thanks!

[FBL]

Hello @coppercrimp ,

Could you confirm the same issue when using pll1_p_ck or AUDIOCLK or HCLK? A screenshot of RCC_CCIPR3 in debug would be helpful.

Do you enter a stop mode in your code?

[coppercrimp]

Hi F.Belaid, thank you for your help with this. As you suggested, I tried using PLL1P to clock the ADF1 peripheral and it works properly. I have not tried AUDIOCLK or HCLK yet, but so far PLL1P and MSIK clocks both work as expected. But PLL3Q still does not work. Both PLL1P and PLL3Q are sourced from and external 12.288MHz quartz crystal.

I used an oscilloscope to probe the ADF1_CCK0 pin (PB3) and no clock appears as an output on this pin when using PLL3Q. I can see a clock signal when using PLL1P or MSIK clock sources. 

I've attached a screenshot of the RCC_CCIPR3 register when PLL3Q is selected as the clock source

One more thing - I do not enter stop mode anywhere in my code. 

Thanks again, and best regards

 

[FBL]

Hello @coppercrimp ,

Thank you for the feedback, I reproduced the issue. I suggest this workaround,

__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL3CFGR_PLL3QEN);
instead of  //ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));

Hope this helps!

Firas

[coppercrimp]

Hi Firas,

Thank you for the suggestion, but unfortunately I'm still having the same issue. I replaced all occurrences of 

ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3));

with

__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL3CFGR_PLL3QEN);

in the file "stm32u5xx_hal_rcc_ex.c". After making the changes, the same problem I reported in my original post still persists. Do you have any other suggestions I might be able to try?

[FBL]

Hello Again @coppercrimp 

Would you please share your IOC file?  It is possible that there is something missing in the configuration of the external crystal (HSE)