STM32U LPTIM Autonomous Mode

[dhs]

I am using the LPTIM3 with LSE

An external input is used to trigger a capture.

The STM32U575  spends most of the time in STOP MODE 2.

To keep the LSE active in the LPTIM use the following instruction:

_HAL_RCC_LPTIM3_CLKAM_ENABLE(); // SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN)

The above statement works in the sense that the LPTIM3 continues its count in STOP MODE 2, but does not update the value of the capture register:

capture_new = LPTIM3->CCR1; // CCR1 doesn't get updates while the STM32 is in STOP MODE 2

 I am missing another register to activate compare/capture module on stop mode?

void MX_LPTIM3_Init(void)
{

  /* USER CODE BEGIN LPTIM3_Init 0 */

  /* USER CODE END LPTIM3_Init 0 */

  LPTIM_IC_ConfigTypeDef sConfig = {0};

  /* USER CODE BEGIN LPTIM3_Init 1 */

  /* USER CODE END LPTIM3_Init 1 */
  hlptim3.Instance = LPTIM3;
  hlptim3.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
  hlptim3.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV1;
  hlptim3.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
  hlptim3.Init.Period = 65535;
  hlptim3.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
  hlptim3.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL;
  hlptim3.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO;
  hlptim3.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO;
  hlptim3.Init.RepetitionCounter = 0;
  if (HAL_LPTIM_Init(&hlptim3) != HAL_OK)
  {
    Error_Handler();
  }
  sConfig.ICInputSource = LPTIM_IC1SOURCE_GPIO;
  sConfig.ICPrescaler = LPTIM_ICPSC_DIV1;
  sConfig.ICPolarity = LPTIM_ICPOLARITY_RISING_FALLING;
  sConfig.ICFilter = LPTIM_ICFLT_CLOCK_DIV1;
  if (HAL_LPTIM_IC_ConfigChannel(&hlptim3, &sConfig, LPTIM_CHANNEL_1) != HAL_OK)
  {
    Error_Handler();
  }
  /* USER CODE BEGIN LPTIM3_Init 2 */
  
  __HAL_RCC_LPTIM3_CLKAM_ENABLE();

  /* USER CODE END LPTIM3_Init 2 */

}

[Sarra.S]

Hello @dhs, 

You need to set the CCxDE bit in the LPTIM_DIER register.

Referring to the RM0456: 

"To operate autonomously in stop mode, the input capture DMA request must be enabled by setting the CCxDE bit in the LPTIM_DIER register. Each time a counter value is captured and available in the LPTIM_CCRx register, the APB
clock is requested by the peripheral and a DMA request is generated. The captured value is then transferred to the SRAM. The CCxIF flag is automatically cleared by hardware once the captured value is read by APB (can be any bus master like CPU or DMA)."