STM32L462 Can not start DMA transfer via SPI.

[MDrak.1]

Enabled DMA2_CLK

SPI3_CLK

set DMA2_CSELR = 0x00000033;

GPIO is set up correctly and has clk enabled

CMAR1 CMAR2 CPAR1 CPAR2 s

Setup interrupts for DMAe Channel 1 and 2 and their priorities

setup spi3 cr1 cr2

DMA2_CNDTR2 DMA2_CNDTR1

RESET Ints with DMA2_IFCR

Followed the examples in order through HAL MXCUBE sample program

final steps

enable RXDMAEN

enable SPI3

enable TXDMAEN

sample program starts at this point, but my code does not

note from reference SPI3_CR2 bit TXDMAEN

Bit 1 TXDMAEN: Tx buffer DMA enable

When this bit is set, a DMA request is generated whenever the TXE flag is set.

Not starting.

[waclawek.jan]

Read out and post SPI and DMA registers content.

JW

[MDrak.1]

This is the state of registers before I set the TXDMAEN bit, which should start the process.

DMA2

ISR 0

IFCR W

CCR1 0X000 0093

   THIS INCLUDES THE FOLLOWING SET BITS

   MINC DIR TCIE EN

CNTDR1 0X0000 0011

CPAR1 0X4001 3C03

CMAR1 0X2000 6F64

CCR2 0X00 2083

   THIS INCLUDES THE FOLLOWING SET BITS

   PL MINC TCIE EN

CNDTR2 0X0000 0011

CPAR2 0X4000 3C03

CMAR1 0X2000 6FDC

CSELR 0X0000 0033

SPI3

CR1 0X0000 0364

   THIS INCLUDES THE FOLLOWING SET BITS

   SSM SSI SPE (BR = 04) MSTR

CR2 0X00001701

   THIS INCLUDES THE FOLLOWING SET BITS

   FRXTH (DS = 1) RXDMAEN

SR 0X0000 0002

   THIS INCLUDES THE FOLLOWING SET BIT

   TXE

CRCPR = 0X07

RXCRCR = 0

TXCRCR = 0

EXTI

IMR1 0XFF82 0100

FTSR1 0X0000 0100

PRI  0X0000 0100

IMR2 0X0000 0187

[waclawek.jan]

> CPAR1 0X4001 3C03

And the DR is at offset 0x0C, i.e. SPI->DR is at 0x40003C0C.

JW

[MDrak.1]

Yes I copied the register value incorrectly. Twice. In my code I had 0x40013c3c then I copied it to my list as 0x40013c03 and the correct value is 0x40003c0c.

I will test with that. Incorrect data register address should stop things from working. Thanks.

[MDrak.1]

I ran the tests with corrected values and had more success. The DMA_Transmit started correctly. However the DMA Receiver was never started. The SPR Status register showed receive FIFO overrun. I could not find any SPI DMA Receive Interrupts that were activated when the transmit was in process or completed. Reviewing the details again.