I'm using the STM32L4 Nucleo board with a N25Q256 SPI Flash attached. I can successfully read and write from the spiflash using the QSPI peripheral + HAL layer in standard SPI mode. However when switching to Quad mode, every so often during a longer read from flash (i.e. 512 bytes) I see a data line rise, and immediately (4nano seconds later) be forced to zero when it should stay high. It seems the MCU is forcing this line to 0, but at this point the SPI flash should be driving all data lines and the MCU should have the data lines as inputs. See pictures below.
This entire read is 512 bytes, and this happens with ~62 bytes left. The data in SPI is known, so i know that DQ0 is correctly transitioning to 1 on this falling clock edge, but for some reason it is incorrectly forced to 0 8 nsec later. Why? All previous 450 bytes are read/clocked out correctly in this particular case. Also shorter reads (12 bytes at a time) seem to work every time.
