STM32L431 Spurious RESET on recent component batches

[sroll]

Hi,

when i use sleep mode, i have a reset problem on STM32L431CCT6 only on recent batches.

I implemented the workaround described in section 2.2.5 of dm00218224-stm32l431xx-device-errata-stmicroelectronics.pdf but without success.

The problem only affects recent batches (# 948, 950). The previous batches seem ok (n ° 745, 928).

Any ideas?

Regards

[TDK]

Is the reset specifically caused by waking and entering stop mode quickly?

Do the reset bits indicate the cause was a BOR reset or by something else?

[sroll]

the reset is caused by iwatchdog but i don't know why. To have the problem, I must have:

 a stm32 from a recent batch

 SW launched without JTAG

 SLEEP mode activated (every ms in my case).

One difficulty is that when I try to debug and connect JTAG, the problem does not occur.

[waclawek.jan]

> the reset is caused by iwatchdog

IWDG?

How is it set up? How do you refresh it, exactly? How are the clocks managed across the stop mode?

Reduce your code to a minimal complete compilable exhibiting the problem,

JW

[Jack Peacock_2]

Check the settings in the option bytes. You may have the flag set to start IWDG immediately after a reset.

Jack Peacock

[sroll]

Yes IWDG.

The IWDG configuration:

• prescaler:16
• window value:4095
• down-counter reload value 4095

=> reset if no kick since 2s

The IWDG is kicked every second

The SLEEP activation is done with the HAL command: HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON,PWR_SLEEPENTRY_WFI)

The STM32 is configured in external clock mode and the clock is always active

[sroll]

I think the IWDG work well. I removed the IWDG activation from my SW to suppress the reset.

With this code, sometimes the UART stops but the other tasks seem to work well and sometimes all the tasks seem to stop.

I will try to reproduce with a minimal code.

[TDK]

Sounds like IWDG is causing the reset and that it's not spurious.

[waclawek.jan]

> The IWDG is kicked every second

Isn't this the case of unstable LSI, as per ES0318 - Rev 5 2.2.8 Unstable LSI when it clocks RTC or CSS on LSE ?

Can you output LSI somehow, to observe?

JW

[sroll]

I already tried with an IWDG prescalar set to 256 and I still have a reset.