STM32L010K8 on/off ADC Vrefint in low power run mode?

[vasilevskialeksandar]

We have product that runs on two AAA batteries based on STM32L010K8 and according documentation this product should consume around 26uA when in low power run mode(32Khz clock source).

Measurement showed that micro consumes around 90uA which is unacceptable due to battery life.

We tried to turn of Vrefint using HAL_PWREx_EnableUltraLowPower(); in test part in code and indeed current consumption is lowered to around 50uA. 

Problem is that we want this scenario:

In low power run mode keep track of the time and each minute:

1)turn ON Vrefint

2)Turn on ADC

3) make measurement of power supply and two other adc channels.

 4) turn OFF Vrefint

5) turn OFF ADC.

Problem is that there is some hidden dependency and function

HAL_PWREx_EnableUltraLowPower() does not turn off Vrefint and current consumption stays at 90uA.

Could you please propose solution how to lower current consumption and find the culprit why it seems Vrefint is not turned off.

Additionally could you please clarify what is needed ADC to work properly in Low power run mode.

In the datasheet for the micro is stated that ADC can not be used in low power run mode but it seems it works fine in reality.

Second things is if HSI16 clock is a must for ADC or not? In CubeMX is direct connection between this clock and the ADC. 

[Bubbles]

Hi @vasilevskialeksandar,

the Vrefint is normally only disabled in Stop mode (and lower) when the ULP bit is set. There is no control to turn it off in Run or LPRun. But Vrefint also doesn't consume 40uA. You need to keep searching for the best power consumption settings. You can use examples for other L0 series MCU, they should work with little extra effort. Take a look at the PWR_LPRUN example for L011 nucleo (in the Cubepackage), also at some AN such as AN4777 and AN4635, which provide valuable tips on power optimization.

Consider using sleep, gating clock to some unused peripherals, running from RAM and powering down the flash, disabling BOR, etc.

BR,

J

[vasilevskialeksandar]

Hi @Bubbles ,

Thanks for the provided guidelines. I rechecked things one by one and found that I forgot that to get 32kHz one needs to set AHB divider to 2 in MSI Range0. I have corrected that but current consumption is still high.

Could you please check why in datasheet for STM32L010K8 in Table 3 on page 15 ADC in Low Power Run Mode is marked with "-" (not available) instead of  "o" or "Y"? 

Also in Figure 2 Clock tree is shown that ADC is clocked by HSI16 line only. According CubeMX ADC can be clocked by peripheral clock (in my case 32Khz) but I am not aware what are the drawbacks of that solution.

Will recheck now powering down unused peripheral and disabling BOR.....

Best Regards,

Aleksandar 

[Bubbles]

Hi @vasilevskialeksandar,

I asked colleague for help and here's what he sent:

Analog reference for the ADC internal voltage regulator
The internal ADC voltage regulator uses a buffered copy of the VREFINT internal voltage reference. This buffer is always enabled when the main voltage regulator is in normal Run mode (MR mode, with the device operating either in Run or Sleep mode).
When the main voltage regulator is in Low-power run mode (LPR mode, with the device operating in Lowpower run, Low-power sleep or Stop mode), this buffer can be disabled and the software must follow the procedure described below to use the ADC:
1. Enter Low-power run mode (the ADC and the internal ADC voltage regulator must both be disabled)
2. Enable the VREFINT internal voltage reference by setting the EN_VREFINT bit in the REF_CTRL register. The VREFINT_RDYF bit must be polled until the voltage reference is ready.
3. Enable the buffer by setting the ENBUF_EN_VREFINT_ADC bit in the REF_CTRL register. The VREFINT_ADC_RDYF bit must be polled until the buffer is ready. The buffer consumption is in the range of 8 uA.
4. Enable the internal ADC voltage regulator by setting the ADVREGEN bit. The ADC is then ready to be used.

It's a little confusing, what I wrote before was about the Vrefint itself, but ADC is not using it directly. It's taking the value from a "buffer" (basically OA). This buffer can be enabled and disabled in LPR mode. So the table 3 is wrong, the ADC can be used in LPR, but not by default, it just needs additional effort.

BR,

J

[Roy-Alex]

1. Enable the ADC clock:

   • Set the ADCEN bit in the RCC_APB2ENR register to enable the ADC clock.

2. Configure the ADC:

   • Set the ADC resolution, sampling time, and other parameters using the ADC registers (e.g., ADC_CFGR1, ADC_CFGR2, ADC_SMPR).

3. Configure the VREFINT:

   • Enable the VREFINT by setting the VREFEN bit in the SYSCFG_CFGR3 register.

4. Configure the power mode:

   • Enter the Run mode by clearing the SLEEPDEEP bit in the Cortex System Control Register (SCB_SCR) to ensure that the processor remains in Run mode during ADC conversions.
   • Enter the low-power Run mode by setting the Low-Power Run (LPRUN) bit in the PWR_CR register.

[waclawek.jan]

Hi @Bubbles ,

> ... ENBUF_EN_VREFINT_ADC bit in the REF_CTRL register

RM0377 in revision history has this to say for Rev.2, May 2015:

changed REF_CTRL into REF_CFGR3

And, amusingly, in the very same entry for the same revision:

Replaced REF_CFGR3 by SYSCFG_CFGR3.

Also:

ENBUF_EN_VREFINT_ADC into ENBUF_VREFINT_ADC

:‑)

But I always wanted to ask, what all bits in SYSCFG_CFGR3 are about. Fancy writing an appnote?

JW

[Bubbles]

Hi @waclawek.jan 

Thanks for the corrections. I did not remember there was a rename. L0 series is still low power champion when configured correctly, but the choice to make every single detail that can save some nanoamperes configurable also made it relatively complex to work with.

I already did several AN about the L0, but now I'm busy with other stuff. It's an established product, effort spent in AN would not be justified.

Sorry

J

[waclawek.jan]

Hi @Bubbles ,

> It's an established product, effort spent in AN would not be justified.

I understand you don't have much decision of what is the focus of your work and I thank you for all your contributions. I also understand that you don't make up the ST policies, but I find this view to be unfortunate. Attention to details may be the one major distinguishing point between ST and its competition, especially the far-eastern bunch.

The L0 has several facets worthy of more attention from marketing point of view, low-power is one of them (and it's not enough just to declare it, as you've said, it's quite tricky to pull it out); EEPROM is other; and I'm sure there are more.

My 2 eurocents' worth.

JW

PS. I can't see nowhere to be explained that SYSCFG_CFGR3 bits are low-power related, except the EN_VREFINT bit.

[Bubbles]

Hi @waclawek.jan,

thanks for understanding.

The SYSCFG bits are not directly power related, they control the internal reference. But in the end, extreme low power consumption is achieved by disabling everything that's not used, actively using clock speed change, use of low power modes and gating the clock to minimize the clock tree. In context of other products the Vrefint buffer power consumption would be negligible, but on L0 the user can actually control it to further the battery life a little.

I agree the L0 is great for many reasons and it will remain in production as long as possible, but now I'm exercising my attention to detail in other products.

Cheers,

J

[dhs]

Hi @Bubbles, 

---

@Bubbles wrote:

Hi @vasilevskialeksandar,

the Vrefint is normally only disabled in Stop mode (and lower) when the ULP bit is set.

---

I couldn't find information about these control bits.

What is the name of these control bits?

Do you have any examples?

Where can I find information about them in the STM32L575 manual?