STM32H7B0 has a lot of spikes on the ADC signals

[OGhis]

Dear,

Setup:
We using a STM32H7B0 100pins.
We use 1 ADC input at 1M samples
Configured as 16bit, differential input, with an offset of 32768.
We use a Vref of 2.5V.
The other side of the differential input is 1/2 of Vref (buffered with a opamp)
To sample the data of the ADC we use a DMA circulaire mode to internal memory.

When we measure our signal we seen many spikes on the samples.
With the scope is the input signal very clean.
Also we use a opamp to buffering the analog signal before it get tot the ADC input.
The opamps we used are LTC6256

We cannot understand why we seen all these spikes.
What are we doing wrong here or is there an explanation for this phenomenon?

Thereby when we changes our sample rate to 100Ksps it has the same effect.
Also when we change the ADC input from differential to single ended.

regards

[waclawek.jan]

> Also we use a opamp to buffering the analog signal before it get tot the ADC input.

This is quite normal, due to the switching sampling capacitor. Depending on the sampling period and the signal source impedance it may settle properly by the end of sampling time.

Show relevant portion of the schematics.

[EDIT]

> The other side of the differential input is 1/2 of Vref (buffered with a opamp)

Note, that differential ADC input has severe limitations as per common mode voltage. See datasheet.

JW

[SofLit]

Hello;

More likely it's related to the phenomena described in the AN2834 / Section 4.4.2 Explanation of the behavior

[OGhis]

Dear,

>> This is quite normal, due to the switching sampling capacitor. Depending on the sampling period and the signal source impedance it may settle properly by the end of sampling time.

We can understand that there are small peaks of ~5-10mV, but here it is sometimes more than 100mV on a scale of 1.25V.
Is there a method what we can use to reduce these spikes?

[waclawek.jan]

You can connect a capacitor to form a capacitive divider, say 0.5nF vs. the cca 6pF of sampling capacitor will give you a peak of cca 1/100 of the voltage difference, that's a few mV. But then your buffer has to be capable of perfectly and stably drive that 0.5nF capacitor, and you are dealing with all the imperfections of that capacitor, too.

As I've said, if your buffer's output impedance times the sampling capacitor capacitance forms a short enough time constant so that by the end of sampling period the sampling capacitor is sufficiently charged, you can ignore the spike.

I've also warned you about the required common mode voltage in differential mode.

JW

[OGhis]

Dear,
we understand this phenomenon and as a solution we should put an external capacitor.
This is not easily possible because we are not measuring DC signals but rather AC signals.
Besides, in the article they talk about small deviations, but we have very large deviations here.
As an example, we are measuring peaks of 45mV on a range of 2.5V. i.e. from our 16 bit adc we only have a good 7 bit left.
Even if we decrease the samplerate also goes to increase the measurement time this continues to occur.
ps we always use the maximum available measurement time for that samplerate.

We think this is really too much of a good thing and really has nothing more to do with the sampling & hold capacitor switch.
Do you have other suggestions?

[OGhis]

Dear,

Here are some measurements

With 470pF on the input of the ADC at 1Msps diff mode (same issue)

With 470pF on the input of the ADC at 100Ksps diff mode (is better but not useful signal yet)

With 470pF on the input of the ADC at 10Ksps diff mode (signal is OK, but sample rate is to low for us)

Without 470pF on the input of the ADC at 100Ksps and diff mode (no changes between extra capacitive load)

Without 470pF on the input of the ADC at 100Ksps and single ended mode (much better, but we must have at least 300Ksps for our project)

Without 470pF on the input of the ADC at 300Ksps and single ended mode (better, but spikes are to high)

So:
- It is better to use the ADC in single ended mode
- At 100Khz or higher sample rates, the spikes are to high
- An external capacitor of 470pF on the input has no real effect on the peaks.

if there is no solution to reduce these peaks below 5mV we see no other solution than to discontinue this MCU.
So we do not understand why it has a 16bit ADC in it and can measure up to 3Msps when there are so many measurement errors, even at 100Ksps or higher

Are there any other ideas SW/HW to reduce these peaks.

[AScha.3]

Hi,

I didn't see anything about the ADC setup, 

So how you set it up?

Most important for good clean signal the sampling time, it has to match your input impedance and the speed you want.

From my tests...: set ADC clock to high frequency, as given in ds. About 30 MHz, afair.

And sampling time to 8.5 or 16 cycles.

And important: do calibration and for using differential input use the differential linearity calibration.

And check: no fast switching pins next or adjacent to the ADC input pins!

Then you will get clean signal.

[OGhis · Accepted solution]

Dear,

Our ADC clock frequency is 48Mhz and Sample time is 8.5 cycle.
8.5 cycle is the maximum we can set at 48Mhz otherwise we cannot a ADC sample rate of 1Msps.

We have found the issue with the spikes on the signal.
We had design the PCB with 2 different ground planes. one for the digital ground and 1 for the analog ground.
The connection between the analog and digital ground was done by a ferrite bead and that was not a good idee.
When replaced with a 0 ohm resistor, the spikes were gone

This is the result at 1Msps:

The signal is now very clean except that we seen now another issue:

We can find this noise 8192 samples.
From where come this:
The ADC has a circular buffer of 16384 (0x4000) samples.
Every DMA half-transfer we write 8192 (0x2000) samples to an large external RAM with an QSPI interface.
The QSPI speed was around 80Mhz, 
The length of the noise is about 500 ADC samples long. 500 samples at 1Msps is about 500µS.
Now if we are going to send these samples through the QSPI we need roughly 500µs for this as well.

The ADC inputs we had chosen are right near the QSPI interface.
We now hope after a PCB adjustments that we measure a very clean signal.

Thanks for the help

[waclawek.jan]

Thanks for coming back with the solution. 

> The connection between the analog and digital ground was done by a ferrite bead and that was not a good idee.

This should not cause issues unless VSSA/VREF- is connected to the digital ground and the input signal is referenced to the analog ground.

However, ground arrangement may be tricky, as we are accustomed to the theoretical notion of one single ground potential, which is not the case in practice.

Please click on "Accept as solution" in that post so that the thread is marked as solved.

JW