STM32H7B0 has a lot of spikes on the ADC signals

[OGhis]

Dear,

Setup:
We using a STM32H7B0 100pins.
We use 1 ADC input at 1M samples
Configured as 16bit, differential input, with an offset of 32768.
We use a Vref of 2.5V.
The other side of the differential input is 1/2 of Vref (buffered with a opamp)
To sample the data of the ADC we use a DMA circulaire mode to internal memory.

When we measure our signal we seen many spikes on the samples.
With the scope is the input signal very clean.
Also we use a opamp to buffering the analog signal before it get tot the ADC input.
The opamps we used are LTC6256

We cannot understand why we seen all these spikes.
What are we doing wrong here or is there an explanation for this phenomenon?

Thereby when we changes our sample rate to 100Ksps it has the same effect.
Also when we change the ADC input from differential to single ended.

regards

[waclawek.jan]

> Also we use a opamp to buffering the analog signal before it get tot the ADC input.

This is quite normal, due to the switching sampling capacitor. Depending on the sampling period and the signal source impedance it may settle properly by the end of sampling time.

Show relevant portion of the schematics.

[EDIT]

> The other side of the differential input is 1/2 of Vref (buffered with a opamp)

Note, that differential ADC input has severe limitations as per common mode voltage. See datasheet.

JW

[SofLit]

Hello;

More likely it's related to the phenomena described in the AN2834 / Section 4.4.2 Explanation of the behavior

[OGhis]

Dear,

>> This is quite normal, due to the switching sampling capacitor. Depending on the sampling period and the signal source impedance it may settle properly by the end of sampling time.

We can understand that there are small peaks of ~5-10mV, but here it is sometimes more than 100mV on a scale of 1.25V.
Is there a method what we can use to reduce these spikes?

[waclawek.jan]

You can connect a capacitor to form a capacitive divider, say 0.5nF vs. the cca 6pF of sampling capacitor will give you a peak of cca 1/100 of the voltage difference, that's a few mV. But then your buffer has to be capable of perfectly and stably drive that 0.5nF capacitor, and you are dealing with all the imperfections of that capacitor, too.

As I've said, if your buffer's output impedance times the sampling capacitor capacitance forms a short enough time constant so that by the end of sampling period the sampling capacitor is sufficiently charged, you can ignore the spike.

I've also warned you about the required common mode voltage in differential mode.

JW