cancel
Showing results for 
Search instead for 
Did you mean: 

STM32H750 Cache ECC

snmunters
Associate II

Hi,

I am trying to trigger a cache ECC error. I referenced AN5342 and this post but Ive had no luck. Please find my code snippet below:

I disable the ECC, invalidate and enable the cache and re-enable the ECC.
I check the IEBR and DEBR registers along with other fault status registers.

Any advice is appreciated. Thanks!

int main(void)
{

	/* USER CODE BEGIN 1 */

	/* USER CODE END 1 */

	/* MCU Configuration--------------------------------------------------------*/

	/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
	HAL_Init();

	/* USER CODE BEGIN Init */

	/* USER CODE END Init */

	/* Configure the system clock */
	SystemClock_Config();

	/* USER CODE BEGIN SysInit */

	/* USER CODE END SysInit */

	/* Initialize all configured peripherals */
	MX_GPIO_Init();
	MX_RTC_Init();
	/* USER CODE BEGIN 2 */
/*caches must be invalidated before being enabled,
	 *and the Cortex-M7 reference manual documents the IEBR/DEBR registers to detect when such errors occur.
	 */
	// Cache is disabled by default

	// Disable ECC
	SCB->CACR = 0x02; //0x01 & SCB_CACR_ECCEN_Msk;

	// Invalidate cache and enable
	SCB_EnableICache();
	SCB_EnableDCache();

	/* Write to Memory */
	volatile uint32_t *mem_addr = (uint32_t *)0x30000000;  // Example address
	*mem_addr = 0xDEADBEEF;  // Write to memory
	int x = *mem_addr; x++;

	// Enable ECC
	SCB->CACR = 0x00;

	// Check IEBR / DEBR registers for ECC error
	while(1){

		// Check IEBR register for Instruction error
		if(*(uint32_t*)0xE000EFB0){
			HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_2, GPIO_PIN_RESET);
		}

		if(*(uint32_t*)0xE000EFB4){
			HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_2, GPIO_PIN_RESET);
		}

		// Check DEBR register for Databank error
		if(*(uint32_t*)0xE000EFB8){
			HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_2, GPIO_PIN_RESET);
		}

		if(*(uint32_t*)0xE000EFBC){
			HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_2, GPIO_PIN_RESET);
		}

		// Memory Management Fault Status Register
		if (SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) {
			HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_2, GPIO_PIN_RESET);
		}

		// Check Bus Fault Status Register
		if (SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) {
			HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_2, GPIO_PIN_RESET);
		}

		// Check Usage Fault Status Register
		if (SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) {
			HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_2, GPIO_PIN_RESET);
		}

	}

	/* USER CODE END 2 */

	/* Infinite loop */
	/* USER CODE BEGIN WHILE */
	while (1)
	{
		/* USER CODE END WHILE */

		/* USER CODE BEGIN 3 */
	}
	/* USER CODE END 3 */
}

 

1 ACCEPTED SOLUTION

Accepted Solutions
SofLit
ST Employee

Hello,

AN5342 / section 2.5 ECC testing applies to the RAM ECC not to the cache ECC and I think not possible to trigger a Cache ECC error by user.

EDIT: confirmed internally: not possible to trigger a cache ECC. This is possible only in RAM ECC.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

View solution in original post

3 REPLIES 3
SofLit
ST Employee

Hello,

AN5342 / section 2.5 ECC testing applies to the RAM ECC not to the cache ECC and I think not possible to trigger a Cache ECC error by user.

EDIT: confirmed internally: not possible to trigger a cache ECC. This is possible only in RAM ECC.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

Check ARM TRM for the cache on the CM7 side.

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

Thank you for checking!

I have attempted to trigger a RAMECC but failed to do so. Do you have any advice? 
STM32H750 RAMECC Testing - STMicroelectronics Community

I appreciate your help.