According to what documentation I can find, ECC is supported in the caches, the TCMs, the system SRAMs, and the Flash.
For caches, the situation is simple: caches must be invalidated before being enabled (whether or not ECC is present), and the Cortex-M7 reference manual documents the IEBR/DEBR registers to detect when such errors occur.
For Flash, the situation is also simple: Flash can be written in whole 256-bit words, either from all-ones to arbitrary or from arbitrary to all-zeroes, and an ECC failure causes DBECCERR or SNECCERR to be set in the Flash SR and the address to appear in ECC_FA*R and a bus fault to be returned to the relevant master.
What’s the situation with TCMs and SRAMs? There appears to be an interrupt (#145) which reports SRAM ECC errors; however, I am not sure whether it’s working: if I try to read from SRAM after a power-up without writing to it first, it appears to be full of random data (suggesting it’s not cleared on power-up reset), yet I don’t see that interrupt become pending (suggesting no ECC failures have happened). These seem inconsistent: if RAM is not cleared at power-up, reading from it should trigger an ECC error. Or am I misunderstanding how the SRAM ECC is supposed to work? Does it need to be enabled somewhere? Similar behaviour seems to happen with the TCMs, except that I can’t even see where an ECC failure is supposed to be reported for TCMs.
The CM7_ITCMCR and CM7_DTCMCR both power up with RMW=1 and RETEN=0. Cortex-M7 technical reference manual section 4.1.7 suggests that, if ECC is equipped, then both RMW and retry must be enabled (RMW=RETEN=1). Furthermore, section 5.8.5 suggests that the TCMs need to be wiped at boot time (though it’s not clear whether that means in software or in hardware). If ECC is *not* equipped, on the other hand, then RMW=0 would give better performance. The STM32H7 documentation suggests that the TCMs have ECC, and yet experimentation suggests that RMW=0 and not wiping at boot works just fine. So what’s going on here? Are ECC errors being reported, but I don’t know where to look to find that out? Or does ST’s ECC implementation actually work with RMW=0, in which case setting that would make sense to improve performance?
Is any of this stuff documented anywhere? The reference manual seems to mention ECC for SRAM in a few places, but not actually explain it anywhere.
