STM32H743 RAMECC behaviour

[KORourke]

I'm trying to use the RAMECC monitoring subsystem on an STM32H743 but there's some behaviour I don't understand. I've read the reference manual (RM0433 rev 7) and application note AN5432, as well as some related forum posts here.

If I set an interrupt enable bit in one of the RAMECC_MxCR registers then I get interrupts even if none of the interrupts are enabled in RAMECC_IER.

So it seems like the interrupt enables in RAMECC_MxCR are independent of the per-monitor interrupt enables in RAMECC_IER.

Is this the intended behaviour? It's unclear to me from the reference manual and AN5432.

[CMYL · Accepted solution]

Hello @KORourke 

yes RAMECC_MxCR are independent from the RAMECC_IER global interrupt bits.

• The RAM system in STM32H743 is dissociated into sectors and each sector can be monitored by a separate ECC controller using RAMECC_MxCR Interrupt Enable bits (x refer to the sector number).
• It is also possible to ECC-monitor all RAM sectors in one shot using RAMECC_IER global interrupt bits. 

Note: you mention AN5432 above, it should be AN5342 .

I will push some inputs to the AN5342 to clarify this point. 

Best regards,

Younes