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KORourke · 2024-05-05

I'm trying to use the RAMECC monitoring subsystem on an STM32H743 but there's some behaviour I don't understand. I've read the reference manual (RM0433 rev 7) and application note AN5432, as well as some related forum posts here.If I set an interrupt...

KORourke · 2023-05-29

I attended the online STM32H5 workshop on Tuesday last week. We were told that the slides and a code for a free STM32H5 Nucleo board would be emailed to us after the workshop. Almost a week later I have still not received either and email to the ad...

KORourke · 2024-06-30

@theHolgi sorry I couldn't reply earlier, I was ill last week. I ended up working out the "interwoven" nature of DTCM RAMECC and ended up with code similar to yours (although in the form of a Zephyr device driver).I was never able to test single erro...

KORourke · 2024-05-02

@Christophe VRIGNAUD Application note AN5432 also mentions that "A special case is DTCM and other memories, which are interleaved" and goes on to explain how to calculate the failing address for those.Are there other memories that are interleaved? I ...

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STM32H743 RAMECC behaviour

Why have STM32H5 workshop materials not been emailed as promised?

Re: FAQ: STM32H7 - How to read RAMECC_MxFAR failing address

Re: FAQ: STM32H7 - How to read RAMECC_MxFAR failing address