I posted the list below as a reply in: https://community.st.com/s/question/0D50X0000A7WOCGSQ4/where-can-i-find-the-adc-input-impedance-of-stm32h743-in-differential-and-singleended-configurations
but the thread seems buried and I think these items should be addressed.
Bumping this up because the current situation has some serious problems.
Issue #1: BOOST bit definition missing in ADC_CR
- Datasheet DS12110, revision 6, Table 184, calls out BOOST as two bits.
- Reference manual RM0433, revision 6, 24.6.3 ADC control register ADC_CR, calls out BOOST at one bit.
From reading stm32h743xx.h, bit 9 of ADC_CR should be BOOST1 and bit 8 should be BOOST0
Issue #2: Radc not specified in data sheet
- Datasheet DS12110, revision 6 is still missing Radc.
- Figure 41 shows RADC and the footnote says it is in Table 87. Unfortunately, it isn't.
- Figure 93 shows RADC and the footnote says it is in Table 184. Unfortunately, it isn't.
Issue #3: Very convoluted to determine how to drive and configure ADC slow channels
- Table 184, page 278 says: Sampling rate for Slow channels (6) is 1.0MSps.
- Table 184, page 279 says: tS Sampling time 1.5 to 810.5 1/fADC
- Table 184, page 279 says: tCONV total conversion time (including sampling time) ts + 0.5 + N/2 where N = conversion resolution
- Footnote 6 says: Slow channel performance is limited to 1 Msps whatever fADC value.
Table 185 calls out the minimum sampling time for a few source impedances (RAIN). Since this is sampling time, this should correspond to tS. However, none of the RAIN values in Table 185 match the RAIN values in Table 184 on the top of page 279!
Looking at the fs data for the direct and fast channels in Table 184 on page 278, I am able to confirm that fs is defined calculated as: fs = fADC / tCONV
This says that for a 14 bit conversion, with an fADC of 36MHz, the sampling time has to be 1us - (0.5 + 14/2)/36MHz = 792ns. Since fADC is 36MHz, this is 28.5 clock cycles. From the reference manual, ADC_SMPR1, the closest sample time selection is 32.5 clock cycles. If I look up 792 ohms for RAIN in Table 185 of the datasheet, there is no entry for 14 bits.
If we used an fADC of 10MHz, the sampling time has to be 1us - (0.5 +14/2)/36MHz = 250ns. Since fADC is 10MHz, this is 2.5 clock cycles. From the reference manual, ADC_SMPR1, this matches one of the sample time selection values. So, maybe this works?
