STM32H730VBT6 SPI port mappable to OCTOSPI interface?

[pkoevesdi]

We have a custom board prototype with a STM32H730VBT6 (LQFP100 package) and a SPI NOR flash memory.

Sadly, this not connected to the OCTOSPIM_P1 port, but to the SPI1_NSS, SPI1_SCK, SPI1_MISO, SPI1_MISO (PA4, PA5, PA6, PB5) port (so, ony 2 data lines are connected, classic SPI).

Now, our application will not fit into internal flash (nor into RAM), so we are captive to use external memory for our program. How can we solve it, except make a new board? Some questions more in detail:

1. Can SPI1 be mapped somehow to OCTOSPI1?

2. Is it (physically or software-wise) possible at all to use that SPI1 connected chip as memory?

    I'd probably would have to reprogram the whole memory protocol (command, address, alternate bytes and data phase...)?

3. What features are possible: DTR? Dual-line SPI? Memory-mapped mode?

    (I think, at least the latter is impossible, if the answer to 1. is no.)

4. Is it possible to execute-in-place from that memory?

    (I think not, if it cannot be brought into memory-mapped mode.)

Can You shed some light, and maybe also confirm or refute my assumptions?

Thank You very much!

[MHoll.2]

No chance on using SPI in any other form than classic SPI (no XIP, no 2 Bit mode etc), apert from copy Your code to RAM and execute it in RAM, You could switch to the pin compatible STM32H725/735 chip, so You have up to 1MByte of internal Flash.

[pkoevesdi]

Thanks a lot!

[pkoevesdi]

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@Pavel A. wrote:

Rust.... :face_with_rolling_eyes:

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It's not my descision, but note to myself and others: that comment led me to this:

"By default, Rust optimizes for execution speed, compilation speed, and ease of debugging rather than binary size"

I did not know that. Thank You!

[Pavel A.]

But C++ does actually the same... not by default, perhaps. And does so for ~ 20 years.

[tjaekel]

I was stepping into the same "trap":
QSPI is not a regular SPI!
You can use QSPI pins and signals only in "half-duplex" mode. QSPI pins and signals do not give you an option to run it like a regular SPI, in "full-duplex" mode (MOSI and MISO in parallel) - not possible.

Yes, annoying, that a regular SPI (e.g. SPI1) cannot share the same pins with QSPI pins, so that it would be possible to toggle between QSPI and regular SPI (what I need as well, "shared pins" for both modes). But not possible (via ALT setting).

Try to find my thread about this issue:
https://community.st.com/t5/stm32-mcus-products/stm32u5xx-qspi-as-regular-spi-not-possible-needs-external-tricks/td-p/629953 

What I did:

• use the QSPI as a "uni-directional" Tx master, in "single-wire SPI mode"
• use a separate SPI peripheral as a SPI Slave, for Rx
• this slave gets the same clock from QSPI master (external pin connections)
• but the Rx (MISO) is done on the SPI slave (the QSPI DIO1 is not used, just DIO0 as SPI MOSI)

This works for me. But it needs a second, regular SPI peripheral in order to implement a full-duplex SPI with QSPI (OCTOSPI peripheral) pins.

[tjaekel]

The OCTOSPI peripheral can NEVER be used in a "full-duplex" mode. No way to have MOSI (DIO0) and MISO (DIO1) transmitting and receiving in parallel at the same time. This is what I mean with "QSPI is not a regular SPI".

It is, on all memory chips, you can change between SPI mode and QSPI. But OCTOSPI on STM32 MCU remains just a "half-duplex" (only one direction).

And the pin mapping is "strange": it does not align properly with MOSI and MISO signals.

So, you need an external signal selector (multiplexer) or the "trick" to use MISO on a separate SPI Slave peripheral: Due to fact, that OCTOSPI acting as SPI Master Tx will not use (not drive) DIO1 (as MISO, it is anyway not the right GPIO pin) - you can connect OCTOSPI DIO1 with the SPI Slave Tx (MISO) signal (externally).

Run OCTOSPI in "single SPI mode" as SPI Tx (MOSI and SCLK), connect SCLK to a SPI slave (SPI1, SPI3, ...) and the route the DIO1 signal as SPI MISO on the Slave device (externally).

[tjaekel]

Here, what I do in order to use OCTOSPI as "regular SPI".

I use OCTOSPI as SPI Master Tx (in "single SPI mode") and SPI3 as SPI Slave Rx: the SCLK goes also to the external SPI slave as well as the SPI Slave SPI3. The SPI3 MISO is taken from the OCTOSPI IO1 (not used on OCTOSPI), which is the external SPI slave MISO signal. The SPI3 does not use the NSS/NCS signal: it runs in SW enable mode.

[tjaekel]

If you need additional external RAM, and you do not can use FSM (e.g. for a DDR memory, SDRAM), OCTOSPI can be used. I use a PSRAM on QSPI (OCTOSPI), works. But such a PSRAM with QSPI is not really large (my one is just 4 MByte, can be a bit larger, but a different package, hard to solder myself).

See the QSPI PSRAM on the bottom.

There is a thread related to PSRAM via QSPI (and DCache):

Solved: STM32U5A5: PSRAM (4MB external RAM) via QSPI (OCTO... - STMicroelectronics Community

[Pavel A.]

@tjaekel Can you write to the PSRAM in memory-mapped mode?

[tjaekel]

Yes, I can.
Just to configure the also the Write command instruction for Memory Mapped mode.
Just: to think about how to "handle" the page wrap (chip wraps to begin of page if a page boundary is crossed).
When caches are enabled - it should not happen that a page boundary is crossed (Cache Line Size).