STM32H723ZG ADC with DMA

[GVG]

Hello everyone,

I am using an STM32H723ZG MCU and wanted to use ADC scan conversion with DMA. I could implement what I wanted there is just one thing I do not fully understand related to it.

I am using ADC3 whose maximal resolution is 12 bit. Based on the reference manual of the MCU, the data of the ADC conversion is stored in a 16 bit register.

When I configure the DMA, I have to choose Word as the data width. Word means 32 bit here.

My question is: Why? Why do I have to set the data width of the DMA 32 bit if the result of the ADC conversion is stored in a 16 bit register?

Thanks in advance,

GVG

[RomainR.]

Hello GVG (Community Member),

Thank you for your request.

In DMA or BDMA Settings tab, you should normally be able to select "Half Word" for DMA Data Size.

Can you confirm ?

Best regards,

Romain.

[GVG]

Hi @RomainR.​ ,

Yes, I can choose Byte or Half-Word as well. However if I do so, then my ADC results are not transferred from peripheral to memory properly.

Maybe I should have asked my question in a more general way. I could look at the MemDataAlignment field in DMA_InitTypeDef structure (both in the source code and in UM2217 HAL Driver description). This is the field in the .ioc file /CubeMX I am asking my question about. UM2217 says that the MemDataAlignment "Specifies the memory data width". Where can I find that what is the memory data width in case of the STM32H723ZG MCU? I couldn't find it either in MCU datasheet or in Reference Manual. (Sorry for the silly question, I'm a beginner.)

Thanks,

GVG

[Piranha]

A good example of why the respective sections of the reference manual should be read first. RM0468 section "15.3.9 Pointer incrementation" explains it. In your case set both sides to 16-bit (half-word) and, of course, provide an array of uint16_t integers.

[MasterT]

You have options to select word - 32 bits because some ADC supports dual mode configuration. Joining two ADC together helps to increase sampling rate twice, and data becomes "packed" as two 16-bits values into one word, so DMA save times to push two conversion results at ones.

Byte size DMA in case ADC configured for lower resolution , 8 or 6 bits. In case faster sampling rate required.

Just configure both ends peripheral & memory to the same width. No error if you will set 32-bits words, just more memory would be necessary - not big deal for small project.

[RomainR. · Accepted solution]

Hello GVG (Community Member),

STM32 are 32 bit architecture, which means that the core, bus and memory widths are 32 bit.

Concerning your firmware, you should be able to make DMA requests from ADC3 on a 2 Bytes size (Half-Word)

I can advise you to look at the following example of the HAL library:

\STM32CubeRepositorySTM32Cube_FW_H7_V1.10.0ProjectsSTM32H735G-DKExamplesADC_DMA_Transfer

You will need to compare your firmware to the ADC and DMA half-word configuration and make sure that your ADC conversion table is declared as follows with the proper alignment in SRAM.

/* Variable containing ADC conversions data */
ALIGN_32BYTES (static uint16_t   aADCxConvertedData[ADC_CONVERTED_DATA_BUFFER_SIZE]);

I hope this helps you.

Thank you in advance for your feedback and best answer.

Regards

Romain, 

[GVG]

Yes, it did help, thank you. Based on the example you referenced I could understand what I was doing in a wrong way and fix it.

Just one last question: Why is the ALIGN_32BYTES needed? It works for me even without it.

[GVG]

Indeed, you are absolutely right. Thank you for your answer.

[Piranha]

If you mean D-cache maintenance, then just aligning an address is not enough.

https://community.st.com/s/question/0D53W00001Z9K9TSAV/maintaining-cpu-data-cache-coherence-for-dma-buffers