Hi there!
I have a problem when using QSPI with NOR flash. Some read commands return data with first 4 bits corrupted.
After investigation, I have found that the issue only appears if there is switch from output to input without dummy cycles.
For example (see picture): I send a 4-line, 1 byte instruction (2 cycles) and read 4-line 3 bytes (6 cycles). I expect IO2 (blue) to switch from output to input prior to clock's (yellow) third falling edge. Instead, it seems to be held at some grey level, that is sometimes sampled as 1 at the third rising edge.
Same issue was observed on STM32H7 with 2 different flash chips, using quad-spi and dual-spi.
Yellow is clock, blue is IO2
I can’t find something similar in errata.
Are some ideas, guys?
Sorry for the confusion. I thought it was self explaining.
Red is SPICLK and blue is SPIO3. They were scaled differently so that the signal can be recognized easily.
The command reads one byte from the slave and sampling was delayed by half cycle, which is why there are 5 clocks.
It's the same problem I think, i.e. SPIO3 and other data pins are not switched to input on time. There is no problem when the first bits of response on data pins are zeros. Only 1's are corrupted when they are the first response bits of SPIOx pins.
More precisely, my suspicion is...
Output block of F7 QSPI controller remains active when input block gets active on 3rd clock. That makes the total impedance of F7 SPIOx very small. 44Ohm is used to supress ringing(for termination purpose). This termination resistor divides ~3V with the output block of F7 SPIOx. Reading level gives 1.2V at this point. On the rising edge of 3rd clock, output block of F7 SPIOx gets inactive and the total impedance of F7 SPIOx is now restored to the impedance of input block of F7 SPIOx pins and so the voltage level gets back to ~3V.
In case of Ilya Balov, the commands ends with 1 and output register has value 1. And it causes the voltage level not to be zero.
equivalent measurement of the same pin with ATSAMV71 and the same device. no half cycle delay for sampling and data pin pulled up. And sampling polarity(or whatever) is different. No problem with the QSPI device.
red is clock and blue is data pin.
My device counts the number of clocks, which is used internally in the device to indicate the offset of device memory. That's why additional clock generated by half cycle delay causes another problem. Half cycle delay does not work for me!!!
I can't agree with your opinion that problem solved if it works by using half cycle delay for sampling. I think even ST engineers can't agree with you.
My data is 1 year old. I'm not ready to provide the data you requested. But better idea came up.
1.2 V voltage is a problem, whichever is responsible for it. It seems possible to determine which is the culprit by measuring the voltage. I will measure the voltages at points 1 and 2 depicted in the picture below. 2 is the output pin of the slave device. We can observe the voltages at points 1 and 2 of SPIOx pins during the 3rd clock. I hope you understand this is not a configuration issue but an input impedance issue.
- 1 and 2 are both close to 3V : good
- 1 is 1.2V and 2 is close to 1.2V (actually a little bit higher)
- 1 is 1.2V and 2 is 3V
case 1 means that we have no problem.
case 2 proves that slave device is doing something wrong.
case 3 proves that F7 QSPI controller is a problem.
Rough physical layout is as below.
Please let me know your opinion about my suggestion.
The data I had is almost 1 year old. Maybe some of the details are not correct. If QSPI_SAMPLE_SHIFTING_HALFCYCLE adds no additional clock, then I can workaround this issue. In your case, one dummy cycle removes this issue. I think I didn't add a dummy cycle. As far as I remember it appears after I enabled the QSPI_SAMPLE_SHIFTING_HALFCYCLE. But I will check it again.
Another problem is the maximum sinking current on both master/slave sides, which is 25 mA for F7. If the outputs of master and slave are both active and they have different logic levels, the current can be bigger than 25 mA. In my setting, it is about 30 mA. Even though the duration of this huge amount of current is very short, it is not good for the QSPI output MOSFET. It has to be taken care of.
One solution for maximum sinking current is to use different modes on master and slave. I didn't test it but I think it will work. I've been using mode 3 on both sides. When slave is changed to use mode 1 with half cycle delay active on master side, then the problematic half cycle will not be used. My slave device support mode1 and mode3.
if only the half of 3rd clock is a problem, it can be skipped by mixing modes (in my thought).
Another solution is to use SPI in my case.
Thanks a lot, mate.
