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STM32H7 | MPUs in dual cores

Zzaaack
Associate III

Hello @ all,

I'm dealing with a project with stm32H755 MCU, as you know it is made of two cores: cortex-M7 and cortex-M4. Keeping in mind I'm using a few peripherals, among which FDCAN, SPI and most importantly lwIP/ETH, I'm trying to put together all the informations I've found online and tested regarding MPUs. I'm going to underline the fact that there are not many, if any, documents regarding MPUS in dual cores, how they should be set and what rules are to be applied.

Let me explain, I suppose that if one of the cores is using a portion of the memory for specific reasons and such area must not be accessed by the other core, I believe i should set the same areas under MPU protection, with access allowed for the core using that memory and without access for the core that won't. Is it correct? On the opposite, should I set only for the core using that memory and the other will "know" automatically not to access that memory area?

I have found many references to the MPU focusing on disabling all accesses to external memories:

 

MPU_InitStruct.Enable = MPU_REGION_ENABLE;

 MPU_InitStruct.BaseAddress = 0x00;

 MPU_InitStruct.Size = MPU_REGION_SIZE_4GB;

 MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS;

 MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE;

 MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE;

 MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE;

 MPU_InitStruct.Number = MPU_REGION_NUMBER0;

 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0;

 MPU_InitStruct.SubRegionDisable = 0x87;

 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;

 

It is often recommended as default. Is it to be placed in both cores? Just in M7 is fine?

Is it useful only in certain conditions but not recommened in others?

I have read the AN4838 but it doesn't explain how to approach MPUs for dual cores.

 

Thanks in advance for the support everyone!

Zack

1 ACCEPTED SOLUTION

Accepted Solutions
TDK
Guru

You don't really need to do anything special, unless you want to explicitly protect areas from being accessed due to bugs in the code. It's fine to leave everything accessible by both cores and use program logic appropriately so that each core only accesses what it's supposed to access.

MPU is useful for setting cacheable/bufferable states of memory, and in cases of safety-critical code it can be used to ensure critical areas aren't protected, but it is not generally used to prevent accesses caused by bugs which shouldn't be taking place.

In other words, there's not really a one-size-fits-all approach or recommendation with the MPU. It's up to you.

If you feel a post has answered your question, please click "Accept as Solution".

View solution in original post

3 REPLIES 3
SofLit
ST Employee

Hello,

Each core has its own MPU. The MPU is a part of the core. So it's up to the user to know the borders of each core access and configure the correspondent MPU accordingly.

So if the MPU config is done on the CM7 side it does mean that it's related to CM7 access. Same thing for CM4.

Hope I answered your question.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
TDK
Guru

You don't really need to do anything special, unless you want to explicitly protect areas from being accessed due to bugs in the code. It's fine to leave everything accessible by both cores and use program logic appropriately so that each core only accesses what it's supposed to access.

MPU is useful for setting cacheable/bufferable states of memory, and in cases of safety-critical code it can be used to ensure critical areas aren't protected, but it is not generally used to prevent accesses caused by bugs which shouldn't be taking place.

In other words, there's not really a one-size-fits-all approach or recommendation with the MPU. It's up to you.

If you feel a post has answered your question, please click "Accept as Solution".
Pavel A.
Evangelist III

Except, maybe, the notorious "speculative execution" issue of the M7 core. Because of it, set up MPU on the M7 side to exclude any shared region assigned to the other core.