[STM32H7] CORTEX_M7 configuration for MPU in CUBEMX

[KhangRtR]

Dear Experts,

I am looking at configuring the CORTEX_M7 section for my custom STM32H743VIT6 based board. Below are the functionalities that I plan to use with the board:

a. Sensors' reading via SPI, I2C, 

b. Communication via UART/USART, USB, Ethernet (LAN8742),

c. LwIP and potentially FreeRTOS

I would like to have your advice on the disabling / enabling of caches and especially the MPU configuration/settings in case :

1. Without external QSPI Flash and external PSRAM,

2. With external QSPI Flash and/or external PSRAM

I took some look at the STM32H7-LwIP-Examples for the NUCLEO-STM32H743 board  and the following h7_lwip_freertos example but there's certain different in terms of number of MPU regions being used as well as their base addresses, sizes and permissions, etc.

Where can I find the information or documentation to correctly configure the above section, please ?

Thanks in advance and best regards,

Khang

[mbarg.1]

Drop FREERTOS+ LWIP (too critical and many bugs oustanding), move to AZRTOS+NetXDuo and we can help. 

[KhangRtR]

Hi @mbarg.1 ,

Sure, I will consider to switch to NetXDuo+AZRTOS if they are really more advantageous than LwIP + FreeRTOS. However, for the moment, I am focusing on correctly configurating the system bsp rather than the middleware.

Best Regards,

Khang

[mbarg.1]

have a look to

How to create a project for STM32H7 with Ethernet and LwIP stack working

@Adam BERLINGER did a good job

[SofLit]

Hello,

AN4839 "Level 1 cache on STM32F7 Series and STM32H7 Series"

AN4839 "Introduction to memory protection unit management on STM32 MCUs"