Hello everyone, I'm using two STM32H503 boards. One is programmed as an I3C controller, the other as an I3C target, and I'm trying to achieve the following sequence on the I3C bus: IBI from target -> Repeated Start -> Private Read
I find two things in RM0492 that may be helpful for my question: One is in Figure 418, there is the following note with 2 asterisks :Repeated start (Sr) if there is a pending transfer to execute and if I3C_DEVRi.SUSP = 0, else stop (P) in push-pull.
The other is that there is a register called I3C device x characteristics register in RM0492. Here is the following description in RM0492, I set bit19 SUSP to 0, so that C-FIFO and TX-FIFO are not flushed after an IBI request.
Based on this description, I preload a private read with C-FIFO before IBI, but I still saw that IBI completes with STOP, and then a START with private read. Is it possible to generate a repeated start after an IBI request? Does Hardware support for this sequence?
