Hi guys, I'm running two differential pairs into two ADC's of an STM32H562RG. The traces are DC blocked by 47nf caps. The ADC's are setup in a master and slave dual simultaneous differential mode, running at 2 MHz each. Data is transferred by DMA. The signal of interest is a baseband signal coming from a tuner IC. The ADC's are timer triggered by TIM2.
VREF on the *562RG is connected to VDDA which is 2.5V (stable)
System clock (adc_hclk) is 240MHz
ADC master clock (adc_ker_ck) is 120 MHz
ADC sample time is 2.5 cycles
With the differential setup I'm expecting both positive and negative ADC channels to be VREF/2. This is true when I select the ADC clock setting to be "ADC_CLOCK_ASYNC_DIV4". To my knowledge this will result in a 30MHz clock coming off the ADC master clock, with 12.5 cycles + 2.5 cycles making it just in time for my 2 MHz sample rate (15 cycles at 30 MHz).
When probing the channels with an oscilloscope I found that the signal (data) coming from the tuner IC is a bit distorted (contains large spikes/random noise) and doesn't contain my signal of interest. This changes when I set the ADC clock source to "ADC_CLOCK_SYNC_PCLK_DIV4". Doubling the ADC clock speed. This also "pulls" the negative channel to just above VSSA and the positive channel to about VREF/2. The signal of interest re-appears on my scope. The ADC measures about 1.25V when the tuner is disabled, giving me a large default offset of about 2047 + 1023.
I have since then tried about every combination I could think of. More cycles per sample, reducing the main clock to as low as 120MHZ. But every time I switch from a synchonous clock to an asynchronous clock the common mode voltage changes and I can't find our why. I'm trying to keep the synchonous clock because I read the possible jitter issue from clock domain syncing.
I'm happy to post my code but I think I'm overlooking something obvious here. Hoping for the "aha-duh" moment in your reply. Kind regards and I appreciate any help.
