STM32H5 bus fault writing DBGMCU_APB1FZR1_DBG_IWDG_STOP

[PieterG]

Today, I suddenly experienced a bus fault on my stm32h563 which I traced down to

DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_IWDG_STOP;

which I use to configure the watchdog to stop when the core has been halted by the debugger.

fault status registers:

SCB->CFSR 0x00008200
SCB->HFSR 0x40000000
SCB->MMFAR 0x44024008
SCB->BFAR 0x44024008

SP 0x2003f048
R0 0x00000000
R1 0x00000002
R2 0x44024000
R3 0x0800813b
R12 0x0000000f
LR 0x080341db
PC 0x0804198e
PSR 0x69000000

Because of this bus fault, the device would not start anymore.

This situation was not resolved by a core reset, nor by flashing new firmware, the only way to resolve it was a power cycle.

What could be the cause of this bus fault?

And how can I avoid this situation in the future?

[Sarra.S]

Hello @PieterG, 

>>the only way to resolve it was a power cycle. 

yes, according to RM, section 59.12.4, "The DBGMCU registers are reset only by a power-on reset. They are accessible to the debugger via the AHB access port at base address 0xE004 4000, and to software at base address 0x4402 4000".

Given that the DBGMCU_APB1LFZR is at address offset 0x08, try to write/ read from the address 0x44024008 to be sure that it's valid and accessible

[PieterG]

That is exactly what I am doing, as you can see in the SCB->BFAR value in my busfault dump: 0x44024008

What I'm doing is the same as what the __HAL_DBGMCU_FREEZE_IWDG() macro does:

#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)

With

#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

and

#define DBGMCU_BASE (0x44024000UL)

Sometimes attempting to set this bit triggers a bus fault, and as a result the MCU gets into an endless fault+reset loop, until a powercycle fixes it.

That is worrying me, we cannot have that in our product.