STM32G474 High speed ADC DAC

[Seren200018]

Dear Community, 

i got two interconnected questions, as i want to build a measurement system that measures and generates sine signals and multi-sine signals with frequencies of up to 1 MHz. For this task i would like to have 10MSPS DAC and ADC acquisition. 

I thought about multiple ways of doing it and would like to hear your thoughts:

1. Just do it all in analog and build a simple lock in amplifier and use an external  signal generator ic
   This would be the method i am currently using but it is fairly limited as it can only generate one frequency at a time or i would have to scale up the analog side.
2. Use the build in ADCs and DACs to generate and measure the signals. 
   The ADC of the G474 is 4MSPS at max res.  would be < 8MSPS in alternating trigger mode.
   Could i use the HRTIM to trigger all ADCs alternating to generate even higher sampling rates?
   Would the DMA be able to handle that? Do i tie all pins together or give everyone a separate opamp to circumvent sampling noise cross talk.
   What is with the DAC? AN4566 says the adc of the G4 series goes up to ~30MSPS but the datasheet only states 1MSPS for external connection? What is now correct? Do i need to internally connect the DAC to the opamp to get the performance coupled with an external opamp?
3. Use an external parallel dac and adc. For this a high number of pins would be necessary and additional hardware. Also would the dma be able to handle a throughput of 120Mbit/s for two gpio channels triggered by a timer running at 100ns trigger frequency?
4. Learn to program FPGAs and use that instead with an external ADC and DAC. Most likely the best option but also the most time consuming one.

Thanks anyone for helping me, :)

[Ozone]

> What is with the DAC? AN4566 says the adc of the G4 series goes up to ~30MSPS but the datasheet only states 1MSPS for external connection?

You need to look at the datasheet of your MCU.
Here the relevant section for the STM32F303:

The settling time, which is caused by internal RC elements, will limit the effective signal bandwidth.
But even if you don't do "full swings" (for which this settling time is defined), I think output signals 1MHz or greater are not really achievable.

[Igor Cesko · Accepted solution]

Hello ,

2) The ADCs can be programmed for different triggers which will be properly equidistantly spread to multiply the sampling rate. Theoretically (because we have inside max 4 ADCs) we can have 4Msps x 5 = 20Msps. Maximum sampling rate takes 15 ADC clock cycles (1.5 cycle is sampling time) - so the triggers must be shifted by 3 ADC clock cycles - we can use 5 timers programmed to output such triggers shifted by 3 ADC clock cycles. I suggest to use same clock for all ADCs and all timers - to be synchronous. In this case all ADCs should use common input: we can connect minimum 4 pins together - ADC12, ADC3, ADC4, ADC5 - because we must use only fast ADC channels (fast channels are 1..5 only).

DAC speed: In AN4566: the ~30Msps is the digital data rate - how fast the firmware can write to data register. But real speed of DAC with external output is 1Msps (analog speed). For faster DAC output you can use internal DACs with internal connection to OPAMP and take output from this OPAMP. The OPAMP bandwidth is ~13MHz - this defines the output speed of internal DACs. We can have 4 fast outputs from internal fast DACs. 
Additionally we can use also slower 1Msps DACs outputs to generate fast signals - but we must use configuration with OPAMP - as described in AN4566 (Figure 2. External OpAmp configuration). But in this case the precision will be degraded due to temperature dependency of internal resistors. Finally we can have 4 fastDAC outputs (with OPAMP) nad additional fast output from slower DACs (with external or internal OPAMPs).

Regarding DMA speed: For ADCs sampling each at 4Msps. We have tested the DMA throughput while we joined ADC12, ADC45 and ADC5. Joining two ADCs has advantage that we can read both results from two ADCs by one 32-bit data register. Theoretically also independent ADC reading (20MHz reading by DMA) should be feasible - each DMA takes 5 AHB cycles => 100MHz will be occupied on the AHB bus.
System clock can be up to 170MHz - but we need to set properly max clock for all ADCs (52MHz max) with 1:1 signal ratio (ADC clock divider must be even). I suggest to use "only" 42.5MHz for ADCs (2.8Msps) with system clock 170MHz (divider by 4). Then we can reach by using 5x ADC the total speed 14.17 Msps. The DMA will have speed: 14.17MHz x 5cycles = 70.8MHz. This is feasible to manage with 170MHz system clock.

DAC speed: DACs can be also joined and updated with DMA. If we will join 2+2 internal DACs then required DMA speed will be 15MHz + 15MHz = 30MHz.

Together with ADC DMA speed and DAC DMA speed we will have approx 100MHz DMA speed. We must take care that this will be maximum DMA usage - another peripheral should not use DMA - to avoid overrun from ADC or DAC.

In case of some problems  - we can optimize the ADC12 + ADC34 +ADC5 (DMA speed will be then 3x2.8MHz x 5 = 42MHz DMA speed).

  Regards

                           Igor

[MasterT]

Is it a typo "G747"? Should be G474.

1. There are two kind of dacs on G4, slow -1 msps and fast 15 msps, read data sheet.

2. Fast dacs have no access to GPIO pin, so always routed via internal OPA.

3. DMA may run at 14 mega words (32-bits) than it starts loosing samples, doing glitches.

   So, dac configured in double-mode (2 conversion per one data transfer to lower dma load) able to get 28 msps.

   Quad dacs 56, but external inverting sum-up amplifier necessary.

4. ADC on G4 is the fastest I've found comparing to F4 /F7 /H7, can reach 11.2 msps in single mode when overclocked to 168 MHz.

   ENOB falls to <7-8-bits, and good driver required for differential input config.

If periodic waveform , no reason to follow Nyquist, you can do "undersampling" - running adc at much lower speed keeping ENOB & SNR as high as possible.  Topic

[Seren200018]

747 is in fact a typo. 474 is correct.