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MasterT
MasterT
Lead II
November 9, 2023
Question

stm32G474re adc performance

  • November 9, 2023
  • 3 replies
  • 9428 views

ADC analog bandwidth tests:

--board nucleo-G474re, on-board voltage reference.

--sampling rate 2.8 msps, free-run mode, 12-bits, 

--156 kHz & 19.47 MHz.  

Approximately at 19 MHz ADC has ENOB < 6 bits, limiting factor seems to be aperture jitter about 120 ps. PLL settings have noticeble impact on the performance, overclocked VCO input  24 MHz (DS max 16 MHz) allows to use lower multiplication factor and as a conseqence better SNR & jitter specification.

div_N: 3
New sys_clock H S E: 172.0 MHz.
Peak: 1183 magn: 1502.1 Total: 22.0 SiNad: 36.672 Enob: 5.799
Peak: 1183 magn: 1501.7 Total: 22.0 SiNad: 36.677 Enob: 5.800
Peak: 1183 magn: 1501.7 Total: 21.5 SiNad: 36.876 Enob: 5.833
div_N: 2
New sys_clock H S E: 174.0 MHz.
Peak: 511 magn: 1502.0 Total: 20.9 SiNad: 37.125 Enob: 5.875
Peak: 511 magn: 1501.6 Total: 21.4 SiNad: 36.919 Enob: 5.840
Peak: 511 magn: 1503.4 Total: 21.0 SiNad: 37.100 Enob: 5.870
div_N: 1
New sys_clock H S E: 168.0 MHz.
Peak: 2577 magn: 1502.1 Total: 15.7 SiNad: 39.594 Enob: 6.285
Peak: 2577 magn: 1502.0 Total: 15.3 SiNad: 39.867 Enob: 6.330
Peak: 2577 magn: 1502.2 Total: 15.6 SiNad: 39.692 Enob: 6.301

 

 

156.25kHz-3.jpg19.47MHz-3.jpgadc test circuits.png

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    3 replies

    LCE
    LCE
    Principal II
    November 9, 2023

    Interesting.
    What ADC exactly is the right most device in the schematic?

    Until now I have only used the STM32 PLL with audio oversampling converters, and these are luckily rather insensitive to the PLL jitter.

    MasterT
    MasterTAuthor
    Lead II
    November 9, 2023

    Read again name of this thread.

    LCE
    LCE
    Principal II
    November 13, 2023

    > Read again name of this thread.

    Okay, but the schematic shows an 8-pin device, that's a little bit misleading.

    MasterT
    MasterTAuthor
    Lead II
    November 13, 2023

    64-pins device better? 

    I'd call it Captcha test, to separate robots alike. 

    waclawek.jan
    waclawek.jan
    Super User
    November 10, 2023

    @MasterT,

    > limiting factor seems to be aperture jitter about 120 ps. PLL settings have noticeble impact on the performance

    Interesting, thanks.

    Are you aware of the common-mode voltage requirement for differential use of the STM32 ADC?

    waclawekjan_0-1699611411923.png

    I'm not sure what the consequences of not maintaining it exactly are - and maybe they become relevant only in some marginal cases - but I thought I'd point it out.

    JW

    MasterT
    MasterTAuthor
    Lead II
    November 10, 2023

    It's  not "visible", but THS7373 is special video driver - not like common OPA. It has some bias circuitry with DC offset internaly, so having 3.3M on inputs it has 1.60V on the outputs.  Differential driver is perfectly balanced.

    I have hard time, to find good adc driver for stm32 product, because of theirs vulnerability to input overdriving - this limits selection down to 3.3V high speed (slew rate especially > 400 V/usec) low distortion (<-50dB 20 MHz) and R2R. Not many parts even highly overpriced from AD or TI could satisfy this requirements. THS7373 is the best, cost only $ 0.5

     

    waclawek.jan
    waclawek.jan
    Super User
    November 11, 2023

    Oh, okay, I did not check that indeed. Thanks.

    JW

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