STM32G474 clock 170 MHz

[koyocik]

Hello,

I use 25 MHz quarz (XRCGB25M000FAN00R0) together with 5.6 pF load capacitors. When I configure clock to 170MHz my program stuck here: while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U).

When I configure clock to 168.75 MHz, then everything work corectly. 

Can someone explain how this problem could be solved?

Thank you for answers.

Best regards

Configuration for 168.75MHz clock:

void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

  /** Configure the main internal regulator output voltage
  */
  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
  RCC_OscInitStruct.PLL.PLLN = 27;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler();
  }
}

 Configuration for 170 MHz clock:

void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

  /** Configure the main internal regulator output voltage
  */
  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV5;
  RCC_OscInitStruct.PLL.PLLN = 68;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler();
  }
}

[Ozone]

It would think not.

While I consider Cube / CubeIDE / CubeMX a "bug fest", I suppose the image above is mostly correct.
Which states that "PLL input clock" is HSE / PLLM and thus 25.000.000 / 5 = 5.000.000.
Here the relevent part of the datasheet from a somewhat similiar MCU, the F407:

As you can see, the PLL input clock is even smaller, but discovery boards come with a 8MHz quartz.
What I meant is called "PLL VCO output" here, which is AFAIK "PLL_IN x PLLN", i.e. (25 / 5) * 68 MHz.

I don't know the G47x nor CubeMX in detail, but I would first check this output with the datasheet.
And second, I don't understand why the CubeMX atumatism would emit so very different numbers (PLL constants) for this small difference in target core clock.

[mƎALLEm]

From: G474 datasheet:

VCO output (25 / 5) * 68 MHz = 340MHz < 344MHz

I don't think this is the issue.

Also with CubeMx, if we set PLL output > 344MHz, it shows this warning:

@koyocik is that possible to decrease the crystal value? or is that possible to feed the OSC_IN with an external clock source in Bypass mode at 25MHz instead of the crystal?

[mƎALLEm]

---

@koyocik wrote:

I found in datasheet that PLL input clock for my STM32G747 can be maximal 16MHz. It means, that I can't use 25MHz crystal to run with my µC ?

---

No. you can reach 48MHz with the external crystal:

[Mike_ST]

Hello,

No, this is the limit after the PLLM divider:

  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV5;

The STM32G474 Nucleo uses a 24Mhz XTAL.

[Ozone]

I might add -  from a logical point of view, problems with the capacitors for the quartz seem unlikely.
Or else the 168.5MHz generation would fail as well.

[mƎALLEm]

---

@Ozone wrote:

I might add -  from a logical point of view, problems with the capacitors for the quartz seem unlikely.
Or else the 168.5MHz generation would fail as well.

---

I'm thinking about the crystal pullability. If the external CL capacitors deviates from the nominal frequency value of the crystal maybe we are at the limit of the VCO output max ..

[koyocik]

I would test 16 MHz crystal this week then I will let you know. Do you know if it's normal that frequency measured on OCS_OUT is different as on OSC_IN ?

[mƎALLEm]

If you mean different in term of frequency value -> No.

Did you observe a difference in the value? if yes how much?

[koyocik]

I tested 2 configurations with frequency 168.75 MHZ.

With PLLM = 2 clock is working but with PLLM equal 4 it's fail.

I meassured OSC_IN signal with oscilloscope and is exactly 25 MHz.

[koyocik]

With lower capacitor value (2pF) on OSC_OUT was 19MHz, with capacitor 5.6pF frequency on OSC_OUT wa 24MHz. In both cases OSC_IN signal had 25MHz.