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STM32G474 clock 170 MHz

koyocik
Associate III

Hello,

I use 25 MHz quarz (XRCGB25M000FAN00R0) together with 5.6 pF load capacitors. When I configure clock to 170MHz my program stuck here: while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U).

When I configure clock to 168.75 MHz, then everything work corectly. 

Can someone explain how this problem could be solved?

Thank you for answers.

Best regards

 

Configuration for 168.75MHz clock:

 

void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

  /** Configure the main internal regulator output voltage
  */
  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
  RCC_OscInitStruct.PLL.PLLN = 27;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler();
  }
}

 

 Configuration for 170 MHz clock:

 

void SystemClock_Config(void)
{
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

  /** Configure the main internal regulator output voltage
  */
  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV5;
  RCC_OscInitStruct.PLL.PLLN = 68;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
  {
    Error_Handler();
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
  {
    Error_Handler();
  }
}

 

 

27 REPLIES 27

@koyocik wrote:

With lower capacitor value (2pF) on OSC_OUT was 19MHz, with capacitor 5.6pF frequency on OSC_OUT wa 24MHz. In both cases OSC_IN signal had 25MHz.


This is the crystal pullability that I was talking about:

mALLEm_0-1741700841352.png

But as the Frequency max you measured is 24MHz, I don't think it's related to the CL and the crystal pullability!

If you replace the PLL input by HSI instead of HSE:

mALLEm_1-1741701018380.png

In this config PLL VCO out freq = 340MHz (same as your 170MHz+crystal). Do you have the same behavior?

 

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

With HSI configuration not working. Doesn't matter if I run with 170MHz or 150MHz or lower. I'm totally don't understand what happen.

Not that it solves your problem ...

But you can start a debug session, disable "run to main", and step through the SystemInit() / SetSysClock() calls in the init code.
This is where clock setup happens (at least it used to).
I would check what is actually written to the RCC registers, and confirm it is stuck waiting for PLLRDY.


@koyocik wrote:

With HSI configuration not working. Doesn't matter if I run with 170MHz or 150MHz or lower. I'm totally don't understand what happen.


That's really weird.. 

Are you sure about your HW espcially the power supply?

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

RCC registers are as follow.

Looks everything same only with PLLM 5 I get timeout.

        while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
          {
            return HAL_TIMEOUT;
          }
        }

Working configuration 168.75 MHz:

1.jpg

Not working confirguration 170 MHz:

2.jpg

My power supply connection looks like that:

1.jpg

As I might have mentioned, I don't use Cube / HAL.
The "old" SPL code would wait for the PLLRDY flag forever, and never time out.
Not sure if that helps, but you could play with the PLL_TIMEOUT_VALUE, or replace it with a "hard" while loop, waiting for the PLLRDY bit.

Anyway, the 168,5MHz and 170MHz values are too close to assume an issue with the quartz itself, surrounding components (like Cs), or the power supply. While the PLL VCO out might play a role, it is just a tiny fraction of the silicon.

The only significant difference between both cases I can spot is PLLM and PLLN, to achieve the desired target core clock by integer multiplication/division from the given input. And while the <25MHz / 5 * 68> configuration does not exceed the datasheet limits, it might nonetheless cause problems (a.k.a. "bug").

I would try a different quartz as suggested, aiming for a lower PLL VCO out frequency (i.e. PLLN value ) to achieve the desired 170MHz.
And for the time being, live with the 168,5MHz ...

I found out problem. I have on the board op amps. One of them generates negative voltage which is applied to ADC input pin (I have zenner diode but after all I have there -0.75V). This negative voltage caused strange behaviour with clock settings. 

Thank you all for the help on this topic!