I brought the sinewave with 120mVpp amplitude as positive input to STM32G431K8 onboard comparator (COMP4). Negative input is internaly taken from DAC. Comparator hardware output is connected to oscilloscope probe (short trace, spring connection) and can bee seen at screen 1 as "red" trace. Comparator have maximum (70mV) hysteresis and oscilloscope data is consistent with this (output transitions are separated by ~60mV). But when i zoom at comparator output transitions, i can see nasty glitches (trace 2 and 3). When i change GPIO slew rate, glithes will disappear as expected. But despite this, they are still present ! If i enable EXTI interrupt from comparator to detect for example falling edge, i can see that IRQ is called often also on rising edge with the same rate as glitches mentioned above. Therefore i believe that glitches are present inside MCU regardless of what is happening outside (if comparator output is on or off, or slew rate i high or low) and therefore i can rule out a faulty layout.
This behavior makes practically impossible to use the comparator to detect slower rising/falling edges using EXTI. Of course i can route comparator into timer and filter out glitches by internal digital filter (or even simply by timer sampling frequency) and use its trigger or input capture interrupt as "virtual" EXTI, or filter comparator outpu by SW. But it is not strightforward and and there are many other limitations associated with it.
It does not depend on whether the DAC output is routed to GPIO or not or DAC buffer enabled or not.
"Noise" on blue traces are measurment artefacts (due poor "blue" probe grounding) - which is evidenced by the screen 4 (minimum slew rate).
As you can see at screen 4 input noise is negligible in comparison to 70mV histeresis.
Comp inputs are filtered by 220pF and loaded by 680R. Signal source is lab. AWG.
Am I doing something wrong or will I have to put up with this behavior ?
Red trace - comparator "hw" output
Blue trace - comparator input
screen 1: general overview
screen 2: Comp HW output on rising edge with maximum GPIO slew rate
screen 3: Comp HW output on falling edge with maximum GPIO slew rate
screen 4: Comp HW output on rising edge with minimum GPIO slew rate (glitch is not visible, but still present inside MCU)
