STM32G4 TIM2 Output Compare No Output internal output state reading

[MC_ONE]

Hi to all, i'm using the TIM2 channel 1 configured as "Output Compare No Output" with mode "Compare on match" and i need to read on the fly its internal logic state as it was a normal output compare with GPIO output.

As far as i understood the related internal line is "tim_oc1ref" but i'm not able to figure out which register contains it's logic state.

Is there a way to read it ?

[waclawek.jan]

No.

JW

[MC_ONE]

That's a huuuge problem for me :face_screaming_in_fear:

Right now i have in place a working code that makes use of TIM2 CH1 OC physical GPIO output readout under its ISR, but due to a project's spec modification we need to use that pin for another purpose, so i need something that determine the OC output state during the execution of TIM2_IRQHandler.

is there a way to read it indirectly?

[waclawek.jan]

Depends on how the Ouptut Compare is set in CCMRx.

If PWM, then simply read TIMx_CNT and compare to value which is in TIMx_CCRx.

JW

[MC_ONE]

Sadly it's not that easy, it's used in Toggle Mode ...

[waclawek.jan]

If it's not too fast, set up DMA triggered from that channel, in circular mode, with even NDTR in given DMA channel. LSB of NDTR will then correspond to the OCxRef.

JW

[Bob S]

Enable the "compare" interrupt and count the number of interrupts, or toggle a variable between 1 and 0 on each interrupt, thus simulating the action that used to happen on the physical pin.

[waclawek.jan]

Another option would be to use the given OCxREF as TRGO, and in a linked timer use the TRGI as external clock. Again, LSB is equivalent to OCxRef of the master.

JW

[MC_ONE]

Hi Bob,

associated ISR is already enabled with a low priority level so it wouldn't be "robust" enough due to high update delay.

There are several ISRs in place, the system works properly even if the above mentioned one is executed within milliseconds but OC toggled output signal MUST be deterministic being read on the fly by an high priority periodic timer ISR.

Right now i'm simply reading the OC output state by mean of GPIOx->IDR register related to used OC output pin.

[MC_ONE]

Hi Jan,

TRGO is currently set to "Compare Pulse (OC1)" as i need a trigger event for both OC output edges (low to high and high to low), OCxREF does not work for me as it produces only one trigger, ie low to high with channel polarity set to high.

That signal is linked to a slave timer programmed as "Output Compare no output" in One Pulse Mode with RCR greater than zero to generate a burst of timed ISR calls, but the discussed toggle mode OC status is not sampled there.