Hello,
For STM32G4 Rev Y:
Errata 2.7.3
Wrong ADC result if conversion done late after calibration or previous conversion
Description
The result of an ADC conversion done more than 1 ms later than the previous ADC conversion or ADC calibration might be incorrect.
Workaround
Perform two consecutive ADC conversions in single, scan or continuous mode. Reject the result of the first conversion and only keep the result of the second.
Errata 2.7.4
ADC channel 0 converted instead of the required ADC channel
Description
The following ADC conversions unduly convert the ADC internal channel 0 instead of the required channel, and as a consequence, they return zero as conversion result:
1. an injected conversion triggered while regular conversion is on-going
2. the master ADC first injected conversion and the slave ADC first regular conversion (after resume) when dual simultaneous or interleaved dual ADC is used
3. the first regular/injected conversion after a regular or injected software STOP (setting ADSTP or JADSTP bit respectively)
4. the first regular or injected conversion following the DMA end of transfer, after the completion of a regular sequence read by the DMA in one-shot mode
Workaround
Apply one of the following measures:
• Depending on the case, insert a dummy conversion:
- at the beginning of the injected sequence (not applicable in injected discontinuous mode, JDISCEN = 1) in the case 1
- after the ADC slave resumes regular conversions in dual simultaneous or interleaved dual ADC mode (not applicable in injected discontinuous mode, JDISCEN = 1) in the case 2
- after stopping the ADC by software in the case 3
- after DMA end-of-transfer in the case 4
• Avoid collisions between injected and regular conversions by using triggered regular conversions or by launching regular conversion at the end of injected sequence in the cases 1 and 2.
• After a regular or injected software STOP, disable the ADC with ADDIS = 1 and enable it again with ADEN = 1. This introduces a hardware dummy conversion (the cases 3 and 4).
I use ADC module in (independent/simultaneous) scan mode with DMA on regular channels. Assume that I have following channel sequence and perform ADC conversions at an interval >1ms with software trigger:
Rank ADC Channel
1 CH1
2 CH1
3 CH2
4 CH2
5 CH3
6 CH3
7 CH4
8 CH4
Should I discard the first two conversions due to ADC Errata 2.7.4 (case 4?)?
Should I discard the first sample for each input (e.g: discard rank 3, use only rank 4) due to ADC Errata 2.7.3? Does it apply to each channel independently, or when conversions done on other channels, it is not applied for the consecutive channels (e.g: discard first two rank, then result of the the following conversions can be used)?
