STM32G0x1 Alternate Functions Clarification

[SHobb.1]

I am designing a board and would like to use the 32 bit timer (TIM2) in encoder mode. Per the block diagram in RM0444:

the inputs to the encoder interface are T1FP1 and TI2FP2, which originate from TIM2_CH1 and TIM2_CH2 (highlighted in yellow). It appears that the TIM2_ETR input is completely unrelated to CH1 and CH2 inputs.

However, in the STM32G0x1 data sheet alternate functions table, I see:

Note, TIM2CH2 is available on pin PA2, and TIM2_CH1_ETR is available on multiple pins (PA0, PA5, PA15). But... which is it? TIM2_CH1 or TIM2_ETR? How can it be both?

I reference register TIM2_AF1 (p. 694 of RM0444), and there are a number of different ETR sources - but none are TIM2_CH1.

What am I missing?

[waclawek.jan]

> which is it? TIM2_CH1 or TIM2_ETR? How can it be both?

Input from that pin is simply connected to both the ETR and CH1 inputs of the TIM module.

JW

[SHobb.1]

Jan,

Thanks for the prompt response. To confirm, the RM implies that external trigger and encoder modes are mutually exclusive (per SMS bits in TIMx_SMCR). So if I connect my external encoder signals to PA0 (TIM2_CH1_ETR) and PA1 (TIM2_CH2), I should be able to configure the registers to enable TIM2 (32 bits) to act in encoder mode. Is that correct?

[waclawek.jan]

> So if I connect my external encoder signals to PA0 (TIM2_CH1_ETR) and PA1 (TIM2_CH2), I should be able to configure the registers to enable TIM2 (32 bits) to act in encoder mode. Is that correct?

Yes.

The TIM2_CH1_ETR combination is quite common in all other STM32, too. This used to be a recurring question one time. The DS used to marke these pins more sanely, but then ST somehow messed it up completely.

An entirely random selection of related threads (you can find more if you want):

https://community.st.com/s/question/0D50X00009XkgkeSAB/stm32f407-tim2ch1etr

https://community.st.com/s/question/0D50X00009XkiSkSAJ/question-about-usage-of-pins-like-tim2ch1etr-tim8ch4bkin2-etc

https://community.st.com/s/question/0D50X00009XkZNISA3/where-is-tim2ch1-on-the-stm32f4-chips

JW

[waclawek.jan]

 #Documentation

#what_a_mess

JW

PS. In the CubeMX xml files, the TIM2_CH1 and TIM2_ETR functions are given separately. That explains the decrease of complaints: most users don't read DS these days.

[SHobb.1]

Thanks again. Have to love documentation inconsistencies...

[ARaid.1]

Do I understand correctly that with an active AF1 remap, the signal from the physical pin is multiplexed to the CH1 input of the timer channel and simultaneously to the ETR input of this timer?

Do I understand correctly that the same AF1 remap also determines the CH1 output of the timer channel on the same physical pin?

[Piranha]

Yes and yes. For STM32 timers an input and output is on the same TIMx_CHx pin.