STM32G071 DMA Will Not Transfer Data to UART1 TDR

[CKafk.1]

I'm trying to operate the USART in DMA tx mode on the STM32G0. I've configured the DMA mux to route the USART1TX dma request to channel 2. I have configured channel 2 to enable TC and TE interrupts, enabled MINC, and set PSIZE & MSIZE as byte. The number of data to transfer is set correctly as well as the MAR and PAR. Obvious things like RCC and GPIO configuration have been checked. The UART registers are configured as expected as well.

However, the DMA number of data to transfer never decrements, despite TXE being high. This makes me think that the dma request is not making it to the correct channel, however I am certain the DMAMUX is configured correctly. Is there something I am missing? My understanding is the DMA transfer should trigger automatically once all the above is configured, so long as the TDR is empty (TXE is high).

[TDK]

Are the UART and DMA stream both enabled? Print out the relevant registers.

[Tesla DeLorean]

Perhaps it wants it to be 16-bit wide at the peripheral register

[CKafk.1]

UART1 is enabled and the DMA stream is enabled as well

Here are the values I'm reading from DMA, DMAMUX, and USART1 registers:

DMA CCR2 = 0x9B

DMA MAR is an address in SRAM

DMA PAR is 0x40013828 (usart1 TDR)

DMA CNDTR2 is 0x4C

all other registers are 0x0

--

DMAMUX C2CR = 0x33

--

USART1 CR1 = 0xD

USART1 CR3 = 0xC0

USART1 BRR = 0x18

USART1 ISR = 0x00600090

All other USART1 registers are 0x0

[CKafk.1]

MSIZE and PSIZE are both set to a byte. The USART1 TDR's data size is 9 bits, with the other 23 bits reserved.

[waclawek.jan · Accepted solution]

I don't have the G0 manual at hand, but isn't this the case of DMAMUX channels being number from 0 and the DMA's from 1?

JW

[CKafk.1]

Using DMAMUX channel 1 instead of 2 fixed this.

Edit: issue has been resolved. Thanks so much - glad it was a simple fix.