Hello,
I am experiencing an interesting problem on the STM32F303VET:
UART1 is used to receive and transmit messages (460800 Baud), DMA1 Channel 4 is used for memory to UART TX buffer transfer, DMA1 Channel 5 for UART RX buffer to memory transfer.
Under situations of high load (both reception and transmission) UART1 will stop outputting messages after two bytes. The majority of transmissions work out fine, however the error happens in every test case, though the time to failure differes between approximately 5s and 120s. The problem seems to be caused by an unintended reset of the DMA enable transmitter (DMAT) Bit in UART 1 control register 3 (USART_CR3).
Above image shows the error:
Trace 1 (orange) shows the TX line of UART1, where only two bytes are transmitted.
Trace 2 (red) shows data on RX line. One can see that no RX takes place at the same time as TX.
Trace 3 shows a debug pin, it is triggered once when DMA transfer is started.
Trace 4 shows another debug pin. It is set HIGH when DMA transfer is started and is set LOW in DMA Transfer finished interrupt triggers (which never happens, because DMA never finishes its transfer, because UART stops emitting data).
A look at the peripheral registers shows the following:
UART 1 CR3 shows that DMAT is off. It was not set to off by software anywhere!
DMA1 Channel 4 Configuration register shows that DMA channel is enabled.
DMA1 Channel 4 count down register shows that there are still 74 (0x4a) bytes remaining to be transmitted.
The problem can be reproduced. Resetting the UART peripheral can reset the error case.
Same procedure was tested on STM32F405 and STM32F469 but could not be reproduced there.
May this be a hardware issue?
If any additional information is needed, let me know.
