2023-09-07 12:36 PM
Hi!
When i run this code in SRAM via the UART bootloader "go command":
asm("cpsid i\n");
// turn off prefetch and set FLASH.latency to 0
cFicen(); cFprften(); uFlatency(0); while (gFlatency()!=0);
// config GPIO (seems to have no effect on power consumption)
((u32*)GPIO[A])[MODER]=-1U;
((u32*)GPIO[A])[OSPEEDR]=0;
((u32*)GPIO[A])[PUPDR]=0;
((u32*)GPIO[C])[MODER]=-1U;
((u32*)GPIO[D])[MODER]=-1U;
((u32*)RCC)[IOPENR]=0;
// switch sysclk to LSI and turn off HSI (initial letter:s=set,c=clr,g=get,u=update)
sClsion(); while (!gClsirdy()); uCsw(LSI); while (gCsws()!=LSI); cChsion();
// go to low power run mode
sPlpr();
// go to low power sleep mode
while (!gPreglpf()); cSCRsleepdeep(); asm("wfi\n");
I get a current of 136uA, where the external parts (PCA9306, SP0504, 2 LDOs, NCP431 voltage clamp) use 20uA...
Even in "run mode"/range2/SRAM/8MHz it used 728uA, instead of the typical 600uA+20uA.
Can someone here say, how i can save those 100uA?
Should I try another board without all those extra parts? Just the STM32G030K6T and a cap of course...?
Thx.
Bye.
Solved! Go to Solution.
2023-09-09 01:05 PM
Hello @Piranha ,
Thank you for your reply.
I found that PWR's clock needs to be enabled in RCC->APBENR1 (PWREN: bit#28). So i added a "sCpwren();"... and it works now: 23µA (with standby mode...)... ChatGPT mentioned that PWR registers need love a clock, too... :face_with_tears_of_joy: :rolling_on_the_floor_laughing:
postscriptum: Now I will try to take care of the compiler optimizations... CMSIS has really some advantages (but i would have to type (or use vim's CTRL+p) a lot...)... GCC seems to be a little bit funny (e. g. it adds a "cmp" after a "subs" in loops, to find out if "subs" resulted in "zero", although "subs" should already take care of that...)... :grinning_face:
Best Regards.
2023-09-07 12:58 PM
Hello @RRIDDICC
For sure, using a board with just the necessary elements will help reducing the energy consommation.
Best regards.
II
2023-09-07 01:34 PM
You didn't even tell what low-power mode are you trying to enter. Anyway, the related issues and proper code is explained there:
Your has many problems also - register accesses are not volatile, inline ASM is missing compiler barriers and nobody knows what other broken code is hidden in all of those strangely named functions. Not using CMSIS provided register definitions and macros doesn't make a sense and leads exactly to such a disaster.
2023-09-07 01:47 PM
@Piranha wrote:You didn't even tell what low-power mode are you trying to enter.
Not using CMSIS provided register definitions and macros doesn't make a sense
2023-09-07 03:34 PM
Ah, you actually already told it... Anyway, read my article because part of it is relevant for all low-power modes.
How can one find the MCU, datasheet, reference manual and this forum, but then not find the provided code?
https://www.st.com/en/embedded-software/stm32cubeg0.html
https://github.com/ARM-software/CMSIS_5/tree/develop/CMSIS/Core/Include
2023-09-09 12:45 PM - edited 2023-09-09 12:47 PM
Hello @Issamos ,
Tthank you for your reply.
I tried a board with the µC and 2 ceramic caps only and the result of the unchange code was the same.
Best regards.
2023-09-09 12:56 PM
2023-09-09 01:05 PM
Hello @Piranha ,
Thank you for your reply.
I found that PWR's clock needs to be enabled in RCC->APBENR1 (PWREN: bit#28). So i added a "sCpwren();"... and it works now: 23µA (with standby mode...)... ChatGPT mentioned that PWR registers need love a clock, too... :face_with_tears_of_joy: :rolling_on_the_floor_laughing:
postscriptum: Now I will try to take care of the compiler optimizations... CMSIS has really some advantages (but i would have to type (or use vim's CTRL+p) a lot...)... GCC seems to be a little bit funny (e. g. it adds a "cmp" after a "subs" in loops, to find out if "subs" resulted in "zero", although "subs" should already take care of that...)... :grinning_face:
Best Regards.