STM32G030 Oversampling Trigger Rate

[Robert Ritchey]

I am a bit confused by the documentation on oversampling and the required trigger rate.  I'd like to do 2 conversions a second on 5 channels using 256x oversampling.  I have the ADC in continuous mode. I am triggering off TIM3 update.  It's not clear to me if I trigger once every half second to get all 256 conversions on all 5 channels or if I have to trigger 256 times each half second.  If there is only one trigger, does the first channel get sampled 256 times and then the second 256 time until the fifth channel? Thanks. 

[PCarn.1]

If your ADC is in continuous mode it will continue looping through the channels once the ADC is initialized. The most processing efficient way to handle this would be to keep the ADCs in continuous mode with DMA enabled, have an interrupt triggered by your timers, then save the ADC value from DMA when in your timer interrupt. This would come at a slight cost to power cause the ADC will always be running. 

Otherwise you would have to get a timer interrupt, trigger an ADC conversion on one channel, wait for that conversion to finish, then trigger the next channel and so on.

[Robert Ritchey]

Hi, thanks but I don't think this answers my question.  I already have the ADC working in continuous mode over the 5 channels.  I have TIM3 Update trigger the ADC at the sample rate I want.  I now want to use oversampling.   The manual is not clear if I trigger it once and the ADC does all 256 samples of each of the 5 channels on its own and I just re-trigger every half second or if I have to trigger it 256 times each half second to get all the oversampling done? 

[PCarn.1]

Yes, you are correct. The oversamping happens automatically when the ADC conversion is triggered.

[TDK · Accepted solution]

> The manual is not clear if I trigger it once and the ADC does all 256 samples of each of the 5 channels on its own and I just re-trigger every half second or if I have to trigger it 256 times each half second to get all the oversampling done? 

This depends on how the TOVS is defined. If not set, a single trigger will cause all 256 samples to be taken. Else, you will need to trigger it 256 times before you get data.

[Robert Ritchey]

Thank you, I was not sure how to interpret that diagram.  It showed DISCEN ==1 and I have this set to 0 and CONT==1 before.  I feel the oversamping section is a bit sparce.  Per the diagram, does this imply that all 256 samples of channel 1 are taken before channel 2 is started? 

[TDK]

If you have CONT=1 then there is never a delay between samples as there is only one trigger to start the process.

> Per the diagram, does this imply that all 256 samples of channel 1 are taken before channel 2 is started? 

It's not really clear. I would strongly guess yes, as the ADC doesn't have data buffers for each channel, so it only makes sense to complete one channel before moving on to the next.

[Robert Ritchey]

Yes, that is what I assumed but it does have the drawback that samples for sequential channels have a significant delay between them.  It is an inexpensive micro though.  I just wish they would expand the explanation of oversampling mode with a few more examples.  Thank you.