stm32f730 , Quad SPI ,how to configure the data shift out on the rising edge of clk and samle one the falling edge

[zhong.1]

stm32f730 , Quad SPI ,i used to communicate to a device ,need 3bits data width.

but how to configure the data shift out on the rising edge of clk and sample the falling edge . like the Stand SPI , we can set CPOL to '0' or '1'?

if not to do , pls provide a mcu to me which have such functions

thanks!

[TDK]

Quad SPI is not just SPI with 4 data lines. It's really a specialized interface for external memories. Sampling is always on the rising edge. Your choices are mode 0 (CPOL=CPHA=0) or mode 3 (CPOL=CPHA=1).

You can chain together 3 SPIs together to get what you want, using one as master and the other two as slaves driven by the master's clock.

[zhong.1]

I know the FPGA can do it ,but i don't famliar with it , so i want to apply on the Mcu . how to Chain 3 SPIs together on one MCU which band as one Master SPI with 3bits data width? or have other such peripheral can do it ，thanks.

[TDK]

Tie all CS lines together. Tie all SCK lines together. Master clock drives the slaves.

[zhong.1]

oh , mabye like this

SPI_1:

MOSI --- data0

SPI_2 :

MISO ---->data1

SPI_3 :

MISO ---->data2

[TDK]

Yes, exactly, plus the CS and SCK lines that I mentioned.

[HDaji.1]

In IOC setting, there is CPOL {low, high}, CPHA {1, 2 edges}.

Can I confirm that (CPOL: 0, CPHA: 0) = (CPOL: low, CPHA: 1 edge)

and (CPOL: 1, CPHA: 1) = (CPOL: high, CPHA: 2 edge)

[TDK]

Yes.

https://en.wikipedia.org/wiki/Serial_Peripheral_Interface