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zhong.1
zhong.1
Associate
Oct 22, 2021 1:40 AM UTC
Question

stm32f730 , Quad SPI ,how to configure the data shift out on the rising edge of clk and samle one the falling edge

stm32f730 , Quad SPI ,i used to communicate to a device ,need 3bits data width.

but how to configure the data shift out on the rising edge of clk and sample the falling edge . like the Stand SPI , we can set CPOL to '0' or '1'?

if not to do , pls provide a mcu to me which have such functions

thanks!

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7 replies

TDK
TDK
Oct 22, 2021 3:17 AM UTC

Quad SPI is not just SPI with 4 data lines. It's really a specialized interface for external memories. Sampling is always on the rising edge. Your choices are mode 0 (CPOL=CPHA=0) or mode 3 (CPOL=CPHA=1).

You can chain together 3 SPIs together to get what you want, using one as master and the other two as slaves driven by the master's clock.

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    HDaji.1
    HDaji.1
    Senior
    Dec 24, 2021 9:25 AM UTC

    In IOC setting, there is CPOL {low, high}, CPHA {1, 2 edges}.

    Can I confirm that (CPOL: 0, CPHA: 0) = (CPOL: low, CPHA: 1 edge)

    and (CPOL: 1, CPHA: 1) = (CPOL: high, CPHA: 2 edge)

    TDK
    TDK
    Dec 24, 2021 3:46 PM UTC

    Yes.

    https://en.wikipedia.org/wiki/Serial_Peripheral_Interface

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    zhong.1
    zhong.1Author
    Associate
    Oct 22, 2021 4:14 AM UTC

    I know the FPGA can do it ,but i don't famliar with it , so i want to apply on the Mcu . how to Chain 3 SPIs together on one MCU which band as one Master SPI with 3bits data width? or have other such peripheral can do it ，thanks.

    TDK
    TDK
    Oct 22, 2021 4:26 AM UTC
    Tie all CS lines together. Tie all SCK lines together. Master clock drives the slaves.
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    zhong.1
    zhong.1Author
    Associate
    Oct 22, 2021 4:59 AM UTC

    oh , mabye like this

    SPI_1:

    MOSI --- data0

    SPI_2 :

    MISO ---->data1

    SPI_3 :

    MISO ---->data2

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